atopile
Official@atopile
Building electronics with code
Agent Skills by atopile
Showing 21 vetted skills indexed across 1 GitHub repositories.
atopile-skills
Maintains SKILL.md documentation files using source-of-truth verification against repository code.
frontend
Enforces architecture, contract, and testing standards for atopile extension webview frontend development.
code-review
Reviews pull requests against repo invariants, tests, and performance criteria with structured scoring.
planning
Plans complex circuit board designs by writing specs as .ato files with requirements and checklists.
agent
Orchestrates checklist-driven implementation of atopile circuit board designs through tool calls.
agent-summary
Generates short live progress summaries from recent agent tool events and build state.
ato
Author and review atopile circuit board designs using the ato declarative hardware language.
Domain Layer
Automate electronics build pipelines to generate Gerbers, BOMs, and PCB layouts.
Graph
Create and manipulate Zig-backed graphs through Python bindings and GraphView.create().
Library
Document the Faebryk component library structure and its generation workflow.
LSP
Provide autocomplete, go-to-definition, hover, and diagnostics for ato files via LSP.
Solver
Simplify and validate Faebryk constraint systems built from Parameters, Literals, and Expressions.
Faebryk
Model and traverse TypeGraph structures with Python-Zig bindings.
Pyzig
Automate Zig to Python bindings for Faebryk modules.
FabLL
Map Python node and trait declarations to a live TypeGraph and instance graph.
Sexp
Parses, formats, and manipulates KiCad S-expressions via Python API.
Dev
Coordinate Zig builds, orchestrated tests, and test artifact consumption.
Skills
Write and maintain SKILL.md files with validated frontmatter and runnable Quick Start sections.
ATO Language
Reference ATO DSL syntax and semantics for editing .ato files and ato.yaml.
Compiler
Parse .ato sources into a linked, self-contained TypeGraph.
Code Review
Guide code reviews by grounding feedback in invariants and test artifacts.
Frequently Asked Questions About atopile
FAQPage SchemaWhat specific hardware engineering tasks does this platform enable?▼
The platform enables the programmatic definition of electronic circuits, allowing engineers to generate PCB layouts, manufacturing-ready Gerbers, and Bills of Materials. It facilitates the validation of component constraints and parameters, ensuring hardware designs adhere to defined electrical invariants before physical production.
Which engineering personas benefit from these capabilities?▼
Hardware engineers, PCB designers, and firmware developers who prefer managing electronic designs through version-controlled source code rather than traditional graphical interfaces. It is specifically designed for teams seeking to integrate hardware development into standard software engineering practices and continuous integration environments.
What are the primary prerequisites for implementing this hardware design environment?▼
Users require a foundational understanding of the ATO domain-specific language and familiarity with KiCad S-expressions. The environment relies on a Zig-backed graph architecture, necessitating a local setup capable of executing the compiler to transform source files into linked TypeGraph structures and final manufacturing artifacts.