ShenShan123ShenShan123Communityยท4 Agent Skills Included

agent-r2g

Automated RTL-to-GDS chip design with signoff and graph datasets

Drives open-source chip design from natural-language specs or RTL through synthesis, place-and-route, and full signoff checks (DRC, LVS, RCX) using OpenROAD, Yosys, and KLayout. Eliminates manual EDA toolchain setup, repetitive flow scripting, and trial-and-error violation fixing with a self-improving repair loop. Converts signed-off layouts into training-ready PyTorch-Geometric graph datasets for machine learning research.
npx skills add ShenShan123/agent-r2g --all -g -y
Available:

Orients the AI agent across the four sub-skills, explaining which skill owns each stage (toolchain setup, RTL acquisition, RTL-to-GDS signoff, graph dataset construction) and how they share environment and learning databases.

All Skills in This Repository (4)

Pure Emerald Level Indicators

Frequently Asked Questions

FAQPage Schema
How to install agent-r2g?โ–ผ

Run `npx skills add ShenShan123/agent-r2g --all -g -y` in your terminal to install all four sub-skills globally.

How to turn RTL into a GDS chip layout automatically?โ–ผ

The signoff-loop skill runs the full OpenROAD flow from your RTL or spec through synthesis, place-and-route, and GDS output, then verifies it with DRC, LVS, and parasitic extraction.

Do I need to install OpenROAD and Yosys manually?โ–ผ

No. The eda-install skill detects your machine and provisions the entire toolchain with one command, using a no-sudo conda path when you lack root access.

Can it build graph datasets for chip design ML models?โ–ผ

Yes. The def-graph skill converts signed-off layouts into PyTorch-Geometric graph datasets with features and labels like congestion, wirelength, timing, and IR drop.

Does it fix DRC and LVS violations on its own?โ–ผ

Yes. A closed learning loop records every fix attempt, learns repair recipes, and applies evidence-ranked fixes automatically on future designs.

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