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masc-ucscmasc-ucscOfficial·1 Agent Skills Included

livehd

Fast hardware compiler for Pyrope and Verilog synthesis

Compiles hardware designs written in Pyrope or Verilog into optimized netlists for ASIC and FPGA synthesis. Runs incremental compilation, logic equivalence checks, and formal verification to catch design errors in seconds. Eliminates slow batch synthesis cycles and manual testbench debugging with live diagnostics and cached build steps.
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npx skills add masc-ucsc/livehd --all -g -y
Available:

Gives the coding agent exact build, test, and debugging commands for LiveHD, plus strict rules on immutable contract tests, fixed sibling dependency paths, and compiler warning policies.

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masc-ucscmasc-ucsc

pyrope

Translate Verilog and Pyrope code within the LiveHD framework.

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Frequently Asked Questions

FAQPage Schema
How to install LiveHD?▼

Run `npx skills add masc-ucsc/livehd --all -g -y` in your terminal to install all skills in this repository globally.

What is LiveHD used for?▼

LiveHD is a hardware compiler infrastructure that turns Pyrope or Verilog designs into synthesized netlists, with fast incremental rebuilds and logic equivalence checking.

How do I write and check Pyrope code?▼

The bundled pyrope skill teaches the full Pyrope language syntax, and the `lhd pyrope lsp` language server gives live compile diagnostics on .prp files in your editor.

Does LiveHD support formal verification?▼

Yes. It includes formal passes that prove assert statements at compile time, plus LEC (logic equivalence checking) against reference Verilog designs.

Can I use LiveHD without hardware design experience?▼

Basic HDL knowledge helps, but the Pyrope skill and live diagnostics guide you through syntax and type errors as you write designs.

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