ai4pb-iteration-issues

Architecture traceability during sprint backlog processing is maintained by linking QA feedback, backlog items, and resolver notes to a central design knowledge graph, ensuring consistent context across architecture-linked artifacts. The skill enforces strict phase-based processing rules for this linkage.

Linking QA feedback and resolver notes to a design knowledge graph is handled by phase-driven backlog processing that enforces global resolution of View references. This ensures only architecture-linked artifacts are affected while updating and preserving context for future iterations.

To start processing iteration issues, load the first unresolved backlog item from the design/tasks/taskandissues_for_LLM.md file and begin processing it within the current architecture knowledge graph context. The system applies phase-based rules from Phase 1 through Phase 4.

Scoped changes to architecture-linked artifacts during defect follow-up are fully supported. The system enforces safe, scoped modifications by applying global resolution of View references and ensuring only architecture-linked artifacts are affected across sprint-level iterations.

Architecture-driven iteration requires phase-based processing rules to enforce evidence resolution and maintain traceability between changes and knowledge graph elements. This phased approach ensures safe, scoped changes to architecture-linked artifacts across sprint iterations.

Sprint-level defect follow-up in enterprise architecture contexts is the primary application. It coordinates architecture-driven iteration issues by handling backlog items, QA feedback, and resolver notes within the design knowledge graph and design-tasks files.