ascendc-mc2-best-practice

Guides design, implementation, and review of Ascend C MC2 multi-card communication-compute fusion operators.

Updated Sep 15, 2026
One-click install
npx skills add https://github.com/WangWindow/CANN-BatchMatMulMaxsum --skill ascendc-mc2-best-practice-wangwindow
Or copy as Structured Prompt for Agent
Please help me install this Agent Skill.
Skill: ascendc-mc2-best-practice
Source: https://github.com/WangWindow/CANN-BatchMatMulMaxsum/tree/main/.agents/skills/ascendc-mc2-best-practice
Command: npx skills add https://github.com/WangWindow/CANN-BatchMatMulMaxsum --skill ascendc-mc2-best-practice-wangwindow

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes scripts (resource) and references (resource) components.

What problem does it solve? Developing Ascend C MC2 operators that fuse multi-card collective communication with on-device computation involves choosing among multiple communication paths (AIV+URMA, MTE, CCU) and coding foundations (blaze-shmem, apace, ascendc-api), each with strict red-line constraints. This Skill provides the decision trees, capability registry, route-specific constraints, and review checklists needed to design, implement, debug, and optimize these fusion operators correctly. ## Core Features & Use Cases - Route Decision & Capability Registry: A decision tree plus a route registry table maps chip (dav-3510/dav-2201), operator type (collective-comm/MoE), invocation form, communication path, and coding foundation to supported, planned, or explicitly unsupported combinations. - Three Coding Foundation Guides: Detailed references for blaze-shmem (SHMEM + Blaze templates), apace (APACE template framework with D1-D6 design contracts and R1-R21 red lines), and ascendc-api (MTE-based MoE Dispatch/Combine with four mandatory constraints). - Requirement Analysis & Quality Gates: Grill protocol with 9 interrogation dimensions, REQUIREMENTS.md template, 14-item quality checklist, and development-readiness gating. - Use Case: When asked to build an AllToAll+Matmul fusion operator on Ascend 950, the Skill routes you to the apace or blaze-shmem path, enforces constraints like banning HCCL high-level APIs, and provides profiling guidance with L2 cache flushing. ## Quick Start Ask the assistant to design or review an MC2 communication-compute fusion operator such as AllToAll+Matmul or MoE Dispatch on Ascend hardware, and it will apply the appropriate route decision tree and constraints.

Frequently Asked Questions about ascendc-mc2-best-practice

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I develop an AllToAll+Matmul fusion operator on Ascend NPU?

First use the decision tree to pick a route: AIV+URMA paths (blaze-shmem or apace foundation) suit collective-communication operators on dav-3510 only. Then consult the capability registry to confirm support, run requirement analysis, and follow the route-specific references for communication APIs, Blaze matmul templates, and pipeline orchestration.

What is the difference between blaze-shmem, apace, and ascendc-api routes?

blaze-shmem manually assembles the SHMEM communication library with Blaze compute templates in a standalone CMake project. apace uses the APACE template framework with reusable block and tiling layers. ascendc-api builds everything on raw Ascend C APIs and targets MTE-based MoE Dispatch/Combine on both dav-2201 and dav-3510.

Why can't I use HCCL high-level APIs in kernel direct-invoke MC2 operators?

HCCL collective communication APIs like Hccl::AllReduce depend on framework-injected communication context, which is unavailable in kernel direct-invoke scenarios. The same applies to AscendC::Matmul high-level APIs. Communication must use SHMEM or APACE interfaces, and matmul must use Blaze templates.

Does MC2 operator development support Ascend 910B (dav-2201)?

Only the ascendc-api route with MTE communication supports dav-2201, covering MoE Dispatch/Combine operators via a compat layer that abstracts window address differences. The AIV+URMA paths (blaze-shmem and apace) are verified only on dav-3510 and are explicitly unsupported on dav-2201.

Why is L2 cache flushing required for MC2 performance profiling?

Without flushing, the previous iteration's B matrix stays resident in L2 cache, inflating MTE2 bandwidth metrics and distorting communication-versus-computation ratios. The reference approach calls a heavy_add_kernel over a buffer larger than L2 capacity before each main kernel launch, then collects data with msprof task-based mode.

When should I choose MTE communication over SHMEM/UDMA for a fusion operator?

MTE communication (AIV+UBMEM) suits routing-intensive workloads like MoE Dispatch/Combine and token distribution, using HCCL-allocated windows with DataCopyPad and state protocols. SHMEM/UDMA suits compute-intensive collective fusions like AllToAll+Matmul where large block transfers dominate.