What problem does it solve? Designing tiling for AscendC SIMT operators differs fundamentally from SIMD operators, and applying SIMD-style UB partitioning to SIMT kernels leads to incorrect block counts, thread misconfiguration, and wasted memory. This Skill provides the correct SIMT-specific methodology for core count splitting, thread count setting, and DCache/UB space allocation. ## Core Features & Use Cases - Core Count Splitting: Computes total blocks as ceil(total output elements / minimum elements per core), with warp (32) alignment and SetBlockDim configuration. - Thread Count Configuration: Enforces constexpr compile-time thread counts (default 1024, max 2048) shared between LAUNCH_BOUND and Simt::Dim3, with guidance by operator type (memory-bound vs compute-bound). - DCache and UB Allocation: Reserves at least 32KB DCache and computes usable UB as 216KB via SetLocalMemorySize. - Use Case: When implementing a SIMT operator on Ascend A2 hardware, use this Skill to determine how many cores to launch, how many threads per core to declare, and how much local memory to reserve. ## Quick Start Ask the AI to design a SIMT tiling strategy for your AscendC operator, including core count, thread count, and DCache allocation.
