ascii-circuit-diagram-creator

Generate ASCII circuit diagrams with a validate-fix workflow and monospace preview.

11|1|Updated Feb 10, 2026
One-click install
npx skills add https://github.com/Takazudo/claude-resources --skill ascii-circuit-diagram-creator
Or copy as Structured Prompt for Agent
Please help me install this Agent Skill.
Skill: ascii-circuit-diagram-creator
Source: https://github.com/Takazudo/claude-resources/tree/main/skills/ascii-circuit-diagram-creator
Command: npx skills add https://github.com/Takazudo/claude-resources --skill ascii-circuit-diagram-creator

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes scripts (resource) and references (resource) components.

What problem does it solve?

Creates clear, unambiguous ASCII circuit diagrams using a generate-validate-fix workflow that enforces golden rules and provides monospace previews.

Core Features & Use Cases

  • Iterative workflow to generate, validate, and fix ASCII circuit layouts
  • Enforces spacing, box delineation, and GND labeling for clean documentation
  • Provides monospace preview rendering to catch crossings and misalignments in advance

Quick Start

Write a connection list and generate an ASCII diagram that satisfies all connections, then preview and refine as needed.

Frequently Asked Questions about ascii-circuit-diagram-creator

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I generate ASCII circuit diagrams for engineering documentation?

To generate ASCII circuit diagrams for engineering documentation, you provide a connection list and the tool iteratively produces a schematic that satisfies all specified connections and validation constraints.

What is the best way to ensure ASCII schematics have correct spacing and alignment?

The best way to ensure ASCII schematics have correct spacing and alignment is using a monospace preview combined with an iterative generate-validate-fix workflow that enforces strict layout rules.

Can I validate ASCII circuit layouts for crossing wires and misalignments before publishing?

Yes, you can validate ASCII circuit layouts for crossings and misalignments before publishing by rendering monospace previews during the generation process to catch rule violations.

How do I fix GND labeling and box delineation errors in ASCII circuit diagrams?

To fix GND labeling and box delineation errors in ASCII circuit diagrams, the validation workflow automatically detects rule violations and iteratively corrects the layout until constraints are met.

Does this ASCII diagram generator work without external dependencies?

Yes, this ASCII diagram generator works without external dependencies, running entirely self-contained to produce validated schematics suitable for documentation and educational materials.

When should I use ASCII circuit diagrams instead of graphical schematics?

You should use ASCII circuit diagrams instead of graphical schematics when creating text-based engineering notes, documentation, or educational materials that require monospace rendering and unambiguous layouts.