assembly-riscv

Inline RISC-V assembly in GCC or Clang uses specific compiler constraints to insert low-level instructions directly into C code. This Skill provides guidance on writing inline assembly while adhering to register conventions and the psABI calling convention for RV32 and RV64 architectures.

The RISC-V psABI calling convention for RV64 defines how functions receive arguments via specific registers and return values. This Skill details the register naming conventions and function call standards required to ensure your assembly code properly interfaces with compiled code.

Setting up QEMU and GDB for RISC-V simulation involves configuring QEMU to emulate an RV32 or RV64 environment and attaching GDB for remote debugging. This Skill guides you through using these tools to simulate and step through your assembly code.

Writing optimized RISC-V assembly for embedded systems often requires using compressed instructions to reduce code size. This Skill covers compressed instructions alongside the standard RV32 and RV64 instruction sets to help you achieve performance-critical and space-efficient low-level development.

You should use RISC-V assembly instead of C when you need to optimize a critical function for maximum performance or precise hardware control in an embedded system. This Skill facilitates such low-level development by detailing instruction sets and calling conventions for direct assembly programming.