assertion-based-verification

What problem does it solve?

SystemVerilog Assertion (SVA) based verification provides a structured way to specify properties and enforce correct behavior, but many designers struggle with choosing the right assertion types, timing, and placement. This Skill delivers best practices, patterns, and debugging guidance to design, place, and validate SVA properties efficiently.

Core Features & Use Cases

• Guidance on selecting assertion types (immediate vs concurrent) for different scenarios such as protocol checks, state machines, and timing requirements.
• Pattern examples for common verification tasks (handshake interfaces, FIFO protocols, data integrity) with clear property templates.
• Debugging and maintenance practices including meaningful naming, assertion coverage, reset handling, and formal-verification friendly properties.
• Practical workflows for placing assertions in interface and datapath modules and augmenting with cover points.

Quick Start

Draft a minimal SVA assertion set for a simple handshake interface to illustrate immediate and concurrent properties.