axion-hdl

Generate AXI4-Lite register interfaces from YAML/JSON or HDL annotations.

2|Updated May 6, 2026

Search Tags:#documentation #yaml #code-generation #hdl #axion-hdl #register-map

Ready to run

npx skills add https://github.com/konosubakonoakua/xilinx-skills --skill axion-hdl

💬 Prompt for ChatGPT / Claude Chat▼

Please help me install this Agent Skill.
Skill: axion-hdl
Source: https://github.com/konosubakonoakua/xilinx-skills/tree/main/axion-hdl
Command: npx skills add https://github.com/konosubakonoakua/xilinx-skills --skill axion-hdl

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve?

Axion-HDL streamlines the creation of AXI4-Lite register interfaces by generating hardware modules, C headers, and documentation from YAML/JSON or HDL annotations, eliminating repetitive manual coding.

Core Features & Use Cases

Generate AXI4-Lite slave modules (VHDL and SystemVerilog) from concise register definitions, including address maps and field descriptions.
Produce consumable artifacts such as C headers, Markdown docs, HTML docs, XML/JSON/YAML registry maps, and optional hierarchy reports for integrated toolchains.
Use cases span FPGA firmware development, RTL/IP integration, and design verification workflows where reliable, repeatable register interfaces are required.

Quick Start

Run axion-hdl with your input specification to produce all target outputs in one command.

Frequently Asked Questions about axion-hdl

High-intent search queries and answers about installing and using this skill.

FAQPage Schema

How do I generate AXI4-Lite register interfaces from YAML?▼

You can generate AXI4-Lite register interfaces from YAML by inputting concise register definitions with address maps and field descriptions to automatically output VHDL and SystemVerilog slave modules.

Can I automatically generate C headers and documentation for FPGA register maps?▼

Yes, you can automatically generate C headers, Markdown, HTML, and XML/JSON registry maps for FPGA register maps from your YAML or HDL annotations in a single processing command.

Does this approach support both VHDL and SystemVerilog for AXI4-Lite slave modules?▼

Yes, AXI4-Lite slave module generation supports both VHDL and SystemVerilog outputs, accommodating diverse FPGA design and RTL/IP integration workflows from the same YAML or JSON input.

What is the best way to automate repeatable register maps for firmware development?▼

Automating repeatable register maps for firmware development is best achieved by defining fields in YAML or HDL annotations to generate consistent hardware modules, C headers, and compatibility maps.

Can I use HDL annotations instead of YAML to define register fields and address maps?▼

Yes, you can use HDL annotations instead of YAML or JSON to define register fields and address maps, producing identical VHDL, SystemVerilog, C header, and documentation outputs.

How do I generate hierarchy reports for integrated FPGA toolchains?▼

You can generate optional hierarchy reports for integrated FPGA toolchains alongside XML, JSON, and YAML compatibility maps by enabling hierarchy support in your register map definitions.