axion-hdl
CommunityAutomate AXI4-Lite register interfaces from YAML/HDL annotations.
Authorkonosubakonoakua
Version1.0.0
Installs0
System Documentation
What problem does it solve?
Axion-HDL streamlines the creation of AXI4-Lite register interfaces by generating hardware modules, C headers, and documentation from YAML/JSON or HDL annotations, eliminating repetitive manual coding.
Core Features & Use Cases
- Generate AXI4-Lite slave modules (VHDL and SystemVerilog) from concise register definitions, including address maps and field descriptions.
- Produce consumable artifacts such as C headers, Markdown docs, HTML docs, XML/JSON/YAML registry maps, and optional hierarchy reports for integrated toolchains.
- Use cases span FPGA firmware development, RTL/IP integration, and design verification workflows where reliable, repeatable register interfaces are required.
Quick Start
Run axion-hdl with your input specification to produce all target outputs in one command.
Dependency Matrix
Required Modules
None requiredComponents
references
💻 Claude Code Installation
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Please help me install this Skill: Name: axion-hdl Download link: https://github.com/konosubakonoakua/xilinx-skills/archive/main.zip#axion-hdl Please download this .zip file, extract it, and install it in the .claude/skills/ directory.
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