bitstream-re

What problem does it solve?

It helps you reverse-engineer FPGA configuration bitstreams by mapping which CRAM bits control specific functionality, so you can reliably read, modify, and regenerate behavior without relying on proprietary assumptions.

Core Features & Use Cases

• Pair-diff CRAM discovery: isolates configuration bits by XOR-diffing RBFs from minimally different designs instead of trying to parse RBF structures directly.
• Routing and codec modeling: builds models for both CRAM geometry and routing behavior, then applies switch/LUT updates via a codec while maintaining XOR-delta semantics.
• Hardware safety and verification workflow: includes guardrails like CRC recomputation and a mandatory end-to-end hardware validation loop to prevent unsafe or non-functional bitstreams.
• SKU/jailbreak probing: tests whether “smaller” SKUs are enabled/disabled primarily by fitter whitelists and verifies physical legality before expanding models.

Quick Start

Use the bitstream-re skill to compute CRAM offsets and routing models for an EP4CE6 by running staged pair-diffs on Quartus-generated RBFs, then codec-replaying the results into an identical silicon-validated bitstream with CRC patched before flashing.