bootstrap_switch

Simulate bootstrapped switches for SAR ADC front-end validation with ngspice.

13|1|Updated Mar 10, 2026

Search Tags:#ngspice #gate-tracking #circuit-simulation #bootstrap-switch #sar-adc

Ready to run

npx skills add https://github.com/Arcadia-1/analog-circuit-skills --skill bootstrap-switch

💬 Prompt for ChatGPT / Claude Chat▼

Please help me install this Agent Skill.
Skill: bootstrap_switch
Source: https://github.com/Arcadia-1/analog-circuit-skills/tree/main/bootstrap_switch
Command: npx skills add https://github.com/Arcadia-1/analog-circuit-skills --skill bootstrap-switch

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill requires ngspice, numpy, matplotlib, and includes assets (resource) components.

What problem does it solve?

Bootstrapped sampling switch simulations validate the gate-voltage tracking VGATE = VIN + VDD, ensure constant on-resistance, and analyze switching topologies for SAR ADC front-ends.

Core Features & Use Cases

Simulate bootstrap NMOS/PMOS and CMOS variants to compare Ron across input VIN ranges.
Analyze clock feedthrough, charge injection, and bootstrap capacitor sizing (CB) effects.
Rapidly size transistors and run end-to-end simulations across technology nodes (180nm/45nm/22nm).

Quick Start

Run the full bootstrap switch simulation suite to generate waveform and Ron plots.

Frequently Asked Questions about bootstrap_switch

High-intent search queries and answers about installing and using this skill.

FAQPage Schema

How do I simulate a bootstrapped switch for a SAR ADC front-end?▼

Bootstrapped switch simulations for SAR ADC front-ends validate gate-voltage tracking and constant on-resistance by running an ngspice workflow with Python-based tooling. You can simulate NMOS, PMOS, and CMOS variants to generate waveform and Ron plots across input voltage ranges.

Why does on-resistance vary in my bootstrapped sampling switch, and how can I analyze it?▼

On-resistance variation in a bootstrapped switch occurs when the gate voltage fails to track the input voltage accurately. You can analyze this by simulating VGATE = VIN + VDD behavior and plotting Ron across the input range using the provided ngspice and matplotlib workflows.

Can I use ngspice and Python to compare bootstrap NMOS, PMOS, and CMOS switch topologies?▼

Yes, you can use ngspice and Python to compare bootstrap NMOS, PMOS, and CMOS switch topologies. The simulations evaluate on-resistance consistency and gate-tracking performance across different input ranges, allowing you to rapidly size transistors and select the best variant for your SAR ADC design.

What is the best way to size transistors and bootstrap capacitors for a SAR ADC sampling switch?▼

The best way to size transistors and bootstrap capacitors for a SAR ADC sampling switch is to run end-to-end ngspice simulations across technology nodes. This allows you to evaluate charge injection, clock feedthrough, and on-resistance consistency to optimize the bootstrap capacitor value.

Does bootstrapped switch simulation work across different technology nodes like 180nm and 22nm?▼

Yes, bootstrapped switch simulation works across 180nm, 45nm, and 22nm technology nodes. You can rapidly size transistors and run end-to-end ngspice simulations to analyze parasitic effects and on-resistance consistency for each specific node.