Port OpenWatt to Bouffalo BL808 and BL618 with Makefile builds and XRAM IPC.
npx skills add https://github.com/open-watt/openwatt --skill bouffalo-port
Please help me install this Agent Skill. Skill: bouffalo-port Source: https://github.com/open-watt/openwatt/tree/main/.claude/skills/bouffalo-port Command: npx skills add https://github.com/open-watt/openwatt --skill bouffalo-port
Bouffalo port for OpenWatt provides end-to-end Bouffalo platform support for building, flashing, and debugging OpenWatt on BL808/BL618 devices, including bare-metal D runtime concerns and dual-core IPC.
Follow the provided Makefile instructions to build for your Bouffalo device and flash to the board.
High-intent search queries and answers about installing and using this skill.
To build and flash bare-metal RISC-V images for Bouffalo BL808 devices, you use Makefile-based build commands targeting BL808 D0 or BL808 M0 cores. This process compiles platform-specific linker and configuration files, generating binaries ready to flash onto the board.
Dual-core XRAM IPC on BL808 is the inter-process communication mechanism linking the D0 and M0 cores via shared XRAM memory regions. It enables coordinated bare-metal startup and runtime operations by mapping specific memory layouts for data exchange between the two RISC-V cores.
Yes, you can use Makefile builds to configure PSRAM and XIP memory regions for BL618. The porting process requires platform-specific linker and configuration files to accurately map these memory regions, ensuring correct bare-metal boot sequences and runtime memory allocation.
Bare-metal RISC-V startup fails during Bouffalo hardware porting usually due to incorrect memory layout mapping or missing boot sequence integration. Debugging requires examining platform-specific linker files, verifying PSRAM versus XIP configurations, and checking interrupt stacks for the BL808 or BL618 target.
The best way to debug RISC-V startup and interrupt stacks on Bouffalo hardware is by analyzing the platform-specific boot sequence and memory layout mapping. You inspect linker configurations for BL808 D0, M0, or BL618 targets to trace bare-metal initialization and resolve IPC or memory conflicts.
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