bscost-net

Plan and execute internet-assisted backside net cost modeling evaluations against HPWL baselines.

8|3|Updated Mar 6, 2026
One-click install
npx skills add https://github.com/Mr-Fang-VLSI/EDAgent --skill bscost-net
Or copy as Structured Prompt for Agent
Please help me install this Agent Skill.
Skill: bscost-net
Source: https://github.com/Mr-Fang-VLSI/EDAgent/tree/main/skills/bscost-net
Command: npx skills add https://github.com/Mr-Fang-VLSI/EDAgent --skill bscost-net

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve?

This skill helps EDA researchers move from single-design intuition to reproducible, multi-design evidence for backside net cost models by planning internet-backed benchmarks, constructing signal and clock model tracks, and running standardized evaluations versus HPWL baselines.

Core Features & Use Cases

  • Benchmark selection: Guided, primary-source web research and a minimum multi-family benchmark set (systolic arrays, Rocket Chip, Gemmini) with pinned commits for reproducibility.
  • Model planning: Dual-track model plans for signal and clock nets with aligned output fields (cost_front, cost_back, delta_cost, min_cost) and theory gating via paired rules.
  • Evaluation & promotion gates: Contract checks, bucketed Pearson/Spearman/sign panels, stability analyses across designs and seeds, and clear promotion rules to move models into active optimization.
  • Artifacts & scripts: Produces contract and bucketed TSV/MD artifacts and leverages provided evaluation scripts for deterministic checks and scorecards.

Quick Start

Use the bscost-net skill to plan and run a multi-design benchmark that compares a backside net cost model against HPWL and produces contract and bucketed scorecards.

Frequently Asked Questions about bscost-net

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I benchmark a backside net cost model against HPWL baselines across multiple designs?

To benchmark backside net cost models against HPWL baselines, select pinned multi-family designs, run dual-track signal and clock evaluations, and generate bucketed TSV/MD scorecards with pass/fail promotion decisions. This ensures reproducible multi-design evidence.

What is backside net cost modeling and when do I need it for EDA evaluation?

Backside net cost modeling estimates routing costs for signal and clock nets on the backside of a design. You need it when validating cost_front, cost_back, and delta_cost metrics to move models into active optimization.

How do I ensure reproducibility when running regression testing for net model evaluation?

Ensure regression testing reproducibility by pinning benchmark design commits, producing contract and bucketed TSV/MD artifacts, and using provided evaluation scripts for deterministic checks across multiple seeds.

Can I use internet-assisted benchmark selection for systolic arrays and Gemmini designs?

Yes, internet-assisted benchmark selection guides primary-source web research to establish a minimum multi-family benchmark set including systolic arrays, Gemmini, and Rocket Chip with pinned commits for reliable evaluation.

What's the best way to measure stability and correlation for net cost models?

Measure stability and correlation by applying the model across multiple designs and seeds, generating bucketed Pearson and Spearman sign panels, and enforcing theory gating via paired rules to validate results.

Why does my backside net cost evaluation fail promotion gates?

Backside net cost evaluations fail promotion gates when contract checks, stability analyses, or bucketed correlation panels do not meet standardized thresholds. Using provided evaluation scripts helps identify specific failures in the scorecards.