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KishoreDamam
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cadence-flow

Automate Cadence ASIC front-end synthesis, simulation, and formal verification workflows.

1|1|Updated Jan 29, 2026
Search Tags:#formal verification#cadence#equivalence checking#genus#asic synthesis#xcelium#jaspergold
One-click install
npx skills add https://github.com/KishoreDamam/VLSI-agkit --skill cadence-flow
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: cadence-flow
Source: https://github.com/KishoreDamam/VLSI-agkit/tree/main/.agent/skills/cadence-flow
Command: npx skills add https://github.com/KishoreDamam/VLSI-agkit --skill cadence-flow

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

It streamlines end-to-end execution of common Cadence ASIC front-end tasks so you can synthesize, simulate, formally verify, and perform equivalence checking with consistent inputs and expected outputs.

Core Features & Use Cases

  • Genus synthesis workflow: Executes syn_generic/syn_map/syn_opt and produces mapped netlists and timing artifacts.
  • Xcelium simulation workflow: Compiles and runs SystemVerilog testbenches using a filelist and a run script for reproducible regressions.
  • JasperGold formal workflow: Analyzes RTL/SVA, sets up clocks/resets, and runs proofs with actionable reporting.
  • Conformal equivalence checking: Supports RTL-to-netlist equivalence checks to catch functional mismatches early.
  • Use Case: When upgrading a block and needing a fast confidence loop, run Genus for a mapped netlist, use Xcelium to validate behavior on gate-level, and apply JasperGold/Conformal to prove properties and equivalence before release.

Quick Start

Ask an AI coding agent to set up a Cadence flow for your project that runs Genus on RTL and constraints, then runs Xcelium with your filelist, and finally launches JasperGold proofs using your assertions.

Frequently Asked Questions about cadence-flow

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I automate Genus synthesis and Xcelium simulation for RTL design verification?▼

Automate Genus synthesis and Xcelium simulation by running syn_generic, syn_map, and syn_opt to produce mapped netlists, then compiling and running SystemVerilog testbenches using a filelist for reproducible regressions.

What is the correct command ordering for Cadence Genus synthesis runs?▼

Cadence Genus synthesis requires correct command ordering, specifically executing read, elaborate, and init_design along with read_sdc before running syn_generic to successfully generate mapped netlists and timing artifacts.

Can I run JasperGold formal verification and Conformal equivalence checking in the same ASIC workflow?▼

Yes, run JasperGold formal verification by analyzing RTL and SVA, setting up clocks and resets, and executing proofs, alongside Conformal for RTL-to-netlist equivalence checks to catch functional mismatches early.

Does Cadence formal verification require specific clock and reset setup for JasperGold property proving?▼

JasperGold formal verification requires tool-specific setup including proper configuration of clocks and resets before running proofs, ensuring actionable reporting for property proving on RTL and SVA inputs.

What is the best way to validate gate-level behavior after generating a mapped netlist with Genus?▼

Validate gate-level behavior after Genus synthesis by running Xcelium simulation workflows that compile and execute SystemVerilog testbenches using your filelist, then apply JasperGold and Conformal to prove properties and equivalence before release.

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