cadence-flow

What problem does it solve?

It streamlines end-to-end execution of common Cadence ASIC front-end tasks so you can synthesize, simulate, formally verify, and perform equivalence checking with consistent inputs and expected outputs.

Core Features & Use Cases

• Genus synthesis workflow: Executes syn_generic/syn_map/syn_opt and produces mapped netlists and timing artifacts.
• Xcelium simulation workflow: Compiles and runs SystemVerilog testbenches using a filelist and a run script for reproducible regressions.
• JasperGold formal workflow: Analyzes RTL/SVA, sets up clocks/resets, and runs proofs with actionable reporting.
• Conformal equivalence checking: Supports RTL-to-netlist equivalence checks to catch functional mismatches early.
• Use Case: When upgrading a block and needing a fast confidence loop, run Genus for a mapped netlist, use Xcelium to validate behavior on gate-level, and apply JasperGold/Conformal to prove properties and equivalence before release.

Quick Start

Ask an AI coding agent to set up a Cadence flow for your project that runs Genus on RTL and constraints, then runs Xcelium with your filelist, and finally launches JasperGold proofs using your assertions.