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claude-skill-verilog

Enforce consistent Verilog and SystemVerilog coding style for Verilator linting and Yosys synthesis.

18|2|Updated Jan 28, 2026
Search Tags:#synthesis#coding-style#testbench#verilator#systemverilog#verilog#yosys
One-click install
npx skills add https://github.com/londey/claude-skill-verilog --skill claude-skill-verilog
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: claude-skill-verilog
Source: https://github.com/londey/claude-skill-verilog/tree/main
Command: npx skills add https://github.com/londey/claude-skill-verilog --skill claude-skill-verilog

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

Inconsistent or unsound Verilog/SystemVerilog code often causes simulation and synthesis mismatches, missed lint warnings, and hard-to-maintain RTL. This guidance consolidates rules and a Verilator-first workflow to make code predictable, testable, and synthesis-friendly.

Core Features & Use Cases

  • Style and naming conventions: Clear rules for active-low suffixes, clock names, one declaration per line, explicit widths, and using default_nettype none to avoid implicit nets.
  • Sequential vs combinational discipline: Enforce always_ff blocks for simple non-blocking register updates and always_comb for all combinational logic, with documented exceptions for memory inference and reset synchronizers.
  • Verification and synthesis workflow: Require testbenches for every module, recommended Verilator linting and simulation flags, and guidance for Yosys-compatible RTL to prevent synthesis failures.
  • Use case: Run as a pre-synthesis checklist to fix style issues, eliminate Verilator warnings, and ensure modules build cleanly with both Verilator and Yosys.

Quick Start

Audit my module.sv for style violations, Verilator warnings, and Yosys compatibility issues and return a prioritized list of fixes.

Frequently Asked Questions about claude-skill-verilog

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I fix Verilator warnings and Yosys synthesis mismatches in my SystemVerilog code?▼

To fix Verilator warnings and Yosys synthesis mismatches, enforce consistent RTL coding style by using default_nettype none, always_ff for sequential non-blocking assignments, and always_comb for combinational logic to ensure simulation and synthesis behavior aligns.

What is the best way to enforce Verilog coding style for synthesis and linting?▼

The best way to enforce Verilog coding style for synthesis is applying rules like one declaration per line, active-low suffixes, explicit widths, and separating sequential and combinational logic into dedicated always blocks before running Verilator linting and Yosys.

Does Yosys support all SystemVerilog constructs for RTL synthesis?▼

Yosys does not support all SystemVerilog constructs for RTL synthesis. You must favor Yosys-compatible RTL constructs, avoid unsupported syntax, and apply a Verilator-first workflow to prevent simulation and synthesis mismatches in your HDL codebase.

How do I prepare a Verilog testbench for Verilator simulation?▼

To prepare a Verilog testbench for Verilator simulation, ensure every module has a corresponding testbench, verify combinational logic uses always_comb blocks, and check that sequential blocks use simple non-blocking register assignments to pass linting checks.

Why does my Verilog code fail Yosys synthesis after passing Verilator linting?▼

Verilog code can fail Yosys synthesis after passing Verilator linting due to simulation and synthesis mismatches from unsupported constructs. Applying a pre-synthesis checklist to favor Yosys-compatible RTL and enforce strict coding style prevents these failures.

Can I use default_nettype none to avoid implicit nets in SystemVerilog modules?▼

Yes, you can use default_nettype none to avoid implicit nets in SystemVerilog modules. Enforcing this rule along with explicit widths and declarations ensures predictable RTL and prevents hidden connectivity errors during Verilator linting and Yosys synthesis.

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