claude-skill-verilog

What problem does it solve?

Inconsistent or unsound Verilog/SystemVerilog code often causes simulation and synthesis mismatches, missed lint warnings, and hard-to-maintain RTL. This guidance consolidates rules and a Verilator-first workflow to make code predictable, testable, and synthesis-friendly.

Core Features & Use Cases

• Style and naming conventions: Clear rules for active-low suffixes, clock names, one declaration per line, explicit widths, and using default_nettype none to avoid implicit nets.
• Sequential vs combinational discipline: Enforce always_ff blocks for simple non-blocking register updates and always_comb for all combinational logic, with documented exceptions for memory inference and reset synchronizers.
• Verification and synthesis workflow: Require testbenches for every module, recommended Verilator linting and simulation flags, and guidance for Yosys-compatible RTL to prevent synthesis failures.
• Use case: Run as a pre-synthesis checklist to fix style issues, eliminate Verilator warnings, and ensure modules build cleanly with both Verilator and Yosys.

Quick Start

Audit my module.sv for style violations, Verilator warnings, and Yosys compatibility issues and return a prioritized list of fixes.