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KishoreDamam
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clean-rtl

Enforce Verilog/SystemVerilog RTL coding standards for modules, naming, resets, and always_ff/always_comb discipline.

1|1|Updated Jan 29, 2026
Search Tags:#code review#rtl#systemverilog#verilog#reset strategy#latch prevention#synthesizability
One-click install
npx skills add https://github.com/KishoreDamam/VLSI-agkit --skill clean-rtl
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: clean-rtl
Source: https://github.com/KishoreDamam/VLSI-agkit/tree/main/.agent/skills/clean-rtl
Command: npx skills add https://github.com/KishoreDamam/VLSI-agkit --skill clean-rtl

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve?

Clean RTL prevents common hardware-description mistakes that lead to inferred latches, simulation bugs, and synthesis/simulation mismatches, while keeping code readable and reviewable.

Core Features & Use Cases

  • Synthesizable RTL hygiene: Standardizes Verilog/SystemVerilog structure choices like module layout, sequential vs combinational blocks, and consistent use of always_ff/always_comb.
  • Latch prevention & reset/port discipline: Enforces complete assignment patterns, reset branch rules, and consistent naming/port ordering to avoid unintended storage and reset misbehavior.
  • PR review checklist: Provides actionable guardrails (anti-pattern list, validation checklist, and inline assertion guidance) so reviewers can quickly verify “RTL correctness first” before deeper architecture work.

Use cases include creating a new RTL module skeleton, reviewing PRs for RTL hygiene issues, and preparing code that will work reliably with lint, synthesis, and downstream skills like FSM design or synthesis guidance.

Quick Start

Use the clean-rtl skill to review your SystemVerilog module for latch inference, incorrect always usage, reset/port naming consistency, and other RTL hygiene issues.

Frequently Asked Questions about clean-rtl

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I prevent inferred latches in SystemVerilog combinational logic?▼

Enforce complete signal assignments across all branches within always_comb blocks to prevent inferred latches in SystemVerilog. The clean-rtl skill provides a validation checklist to verify complete assignment patterns and eliminate unintended storage elements.

What is the correct reset strategy for synthesizable Verilog modules?▼

A correct synthesizable Verilog reset strategy requires consistent reset branching and uniform port naming conventions. The clean-rtl skill enforces reset branch rules and consistent reset styles to prevent misbehavior and simulation-to-synthesis mismatches.

How do I review a Verilog PR for simulation and synthesis mismatches?▼

Review a Verilog PR for mismatches by checking RTL hygiene, latch prevention, and always_ff/always_comb discipline. The clean-rtl skill provides an anti-pattern list and validation checklist to quickly verify RTL correctness before deeper architecture review.

Does clean-rtl work with standard Verilog or only SystemVerilog?▼

Clean-rtl works with both standard Verilog and SystemVerilog, standardizing module structure and sequential versus combinational discipline. It enforces synthesizable coding standards regardless of whether you use Verilog or SystemVerilog syntax.

What are common RTL coding anti-patterns that cause synthesis failures?▼

Common RTL anti-patterns causing synthesis failures include incomplete assignments leading to latches, incorrect always block usage, and inconsistent reset styles. The clean-rtl skill identifies these anti-patterns and provides inline assertion guidance to prevent them.

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