clean-rtl

What problem does it solve?

Clean RTL prevents common hardware-description mistakes that lead to inferred latches, simulation bugs, and synthesis/simulation mismatches, while keeping code readable and reviewable.

Core Features & Use Cases

• Synthesizable RTL hygiene: Standardizes Verilog/SystemVerilog structure choices like module layout, sequential vs combinational blocks, and consistent use of always_ff/always_comb.
• Latch prevention & reset/port discipline: Enforces complete assignment patterns, reset branch rules, and consistent naming/port ordering to avoid unintended storage and reset misbehavior.
• PR review checklist: Provides actionable guardrails (anti-pattern list, validation checklist, and inline assertion guidance) so reviewers can quickly verify “RTL correctness first” before deeper architecture work.

Use cases include creating a new RTL module skeleton, reviewing PRs for RTL hygiene issues, and preparing code that will work reliably with lint, synthesis, and downstream skills like FSM design or synthesis guidance.

Quick Start

Use the clean-rtl skill to review your SystemVerilog module for latch inference, incorrect always usage, reset/port naming consistency, and other RTL hygiene issues.