clock-domain-crossing

Community

Make CDC transfers safe and timing-correct.

AuthorKishoreDamam
Version1.0.0
Installs0

System Documentation

What problem does it solve?

Clock-domain-crossing (CDC) techniques prevent metastability, data corruption, and CDC tool violations when signals move between asynchronous or unrelated clock domains.

Core Features & Use Cases

  • CDC pattern selection: choose the right approach for single-bit synchronizers, multi-bit async FIFOs, req/ack handshakes, pulse/toggle synchronizers, and reset synchronizers.
  • Robust RTL guidance: implement safe synchronizer structures with correct attributes (e.g., ASYNC_REG) and avoid known anti-patterns like synchronizing raw binary multi-bit buses.
  • SDC/constraint correctness: apply timing constraints that bound CDC arrival time using set_max_delay -datapath_only and use appropriate reset handling/waivers when tools legitimately flag async assertions.
  • Validation checklist: verify the design meets CDC correctness requirements before declaring the work complete.

Quick Start

Use the clock-domain-crossing skill to identify the correct CDC architecture for your specific crossing and generate the RTL patterns and SDC constraints to match it.

Dependency Matrix

Required Modules

None required

Components

references

💻 Claude Code Installation

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Please help me install this Skill:
Name: clock-domain-crossing
Download link: https://github.com/KishoreDamam/VLSI-agkit/archive/main.zip#clock-domain-crossing

Please download this .zip file, extract it, and install it in the .claude/skills/ directory.
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