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KishoreDamam
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clock-domain-crossing

Select safe clock-domain-crossing structures for asynchronous signal transfers.

1|1|Updated Jan 29, 2026
Search Tags:#cdc#timing closure#metastability#synchronizers#async fifo#req ack handshake#sdc constraints
One-click install
npx skills add https://github.com/KishoreDamam/VLSI-agkit --skill clock-domain-crossing
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: clock-domain-crossing
Source: https://github.com/KishoreDamam/VLSI-agkit/tree/main/.agent/skills/clock-domain-crossing
Command: npx skills add https://github.com/KishoreDamam/VLSI-agkit --skill clock-domain-crossing

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve?

Clock-domain-crossing (CDC) techniques prevent metastability, data corruption, and CDC tool violations when signals move between asynchronous or unrelated clock domains.

Core Features & Use Cases

  • CDC pattern selection: choose the right approach for single-bit synchronizers, multi-bit async FIFOs, req/ack handshakes, pulse/toggle synchronizers, and reset synchronizers.
  • Robust RTL guidance: implement safe synchronizer structures with correct attributes (e.g., ASYNC_REG) and avoid known anti-patterns like synchronizing raw binary multi-bit buses.
  • SDC/constraint correctness: apply timing constraints that bound CDC arrival time using set_max_delay -datapath_only and use appropriate reset handling/waivers when tools legitimately flag async assertions.
  • Validation checklist: verify the design meets CDC correctness requirements before declaring the work complete.

Quick Start

Use the clock-domain-crossing skill to identify the correct CDC architecture for your specific crossing and generate the RTL patterns and SDC constraints to match it.

Frequently Asked Questions about clock-domain-crossing

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I prevent metastability when transferring signals across asynchronous clock domains?▼

To prevent metastability in clock-domain-crossing transfers, you must use appropriate synchronizer structures for single-bit control signals and multi-bit bus transfers via async FIFOs or req/ack handshakes. Correct CDC pattern selection ensures signal stability across unrelated clock rates.

What is the correct SDC constraint for clock-domain-crossing timing closure?▼

For clock-domain-crossing timing closure, apply SDC constraints using set_max_delay -datapath_only to bound CDC arrival times. This constraint approach correctly handles asynchronous paths without requiring traditional timing analysis across unrelated clock domains.

Why should I not synchronize a raw multi-bit binary bus across clock domains?▼

Synchronizing raw binary multi-bit buses across clock domains causes data corruption because individual bits settle at different times. Instead, use dedicated CDC structures like async FIFOs or req/ack handshakes to ensure coherent multi-bit data transfers.

How do I implement safe reset deassertion synchronization in RTL?▼

Safe reset deassertion synchronization requires implementing reset synchronizer structures with correct RTL attributes like ASYNC_REG. This ensures the reset signal deasserts synchronously to the target clock domain, preventing metastability during system initialization.

When do I need a pulse synchronizer versus a toggle synchronizer for CDC control signals?▼

Use pulse synchronizers for clock-domain-crossing when transferring single-cycle pulses between domains, and toggle synchronizers for continuous control signals. Both require appropriate ASYNC_REG attributes to ensure safe synchronization across unrelated clock rates.

Does clock-domain-crossing validation require specific RTL attributes to avoid CDC tool violations?▼

Yes, CDC validation requires correct ASYNC_REG attributes on synchronizer flip-flops to avoid tool violations. Additionally, apply CDC-appropriate SDC constraints and use reset handling waivers when tools legitimately flag asynchronous assertions.

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