control-loop

Designs, discretizes and validates digital control loops for power electronics simulators.

Updated Apr 7, 2026

Search Tags:#pwm #discretization #anti-windup #power-electronics #digital-control #zoh #tustin

Ready to run

npx skills add https://github.com/lgili/skillex --skill control-loop

💬 Prompt for ChatGPT / Claude Chat▼

Please help me install this Agent Skill.
Skill: control-loop
Source: https://github.com/lgili/skillex/tree/main/skills/control-loop
Command: npx skills add https://github.com/lgili/skillex --skill control-loop

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes scripts (resource) and references (resource) components.

What problem does it solve?

Digital control loops for discrete-time power converters are complex to design, discretize, and validate, often leading to unstable or inefficient performance in simulation environments.

Core Features & Use Cases

Structured workflow for modeling, discretizing, implementing, and validating digital controllers (voltage-mode and current-mode) for PWM converters.
Guidance on ZOH, computational delay, anti-windup, and PWM timing to ensure robust stability and correct loop gain.
Real-world use cases include designing digital controllers for buck/boost converters and verifying performance against standard references.

Quick Start

Start by installing the skill and running the stability analysis script to validate your controller against a test plant.

Frequently Asked Questions about control-loop

High-intent search queries and answers about installing and using this skill.

FAQPage Schema

How do I discretize a digital control loop for a power electronics simulator?▼

To discretize a digital control loop for power electronics, apply Tustin discretization with prewarping or ZOH polynomial approximations to convert continuous-time plant models into discrete-time representations. This ensures accurate frequency response matching for simulation.

Why does my digital voltage-mode controller go unstable in a PWM converter simulation?▼

Digital voltage-mode controllers often go unstable in PWM converter simulations due to unmodeled ZOH delays, PWM timing mismatches, or missing anti-windup logic. Analyzing the open-loop T(z) transfer function identifies phase margin issues causing instability.

What is the best way to implement anti-windup in a discrete-time current-mode controller?▼

The best way to implement anti-windup in a discrete-time current-mode controller is to integrate saturation limits into the digital control loop structure during modeling. This prevents integrator overflow and maintains robust stability under PWM timing constraints.

Can I use Tustin discretization with prewarping for averaged plant models in C++?▼

Yes, you can use Tustin discretization with prewarping for averaged plant models in C++ to preserve critical frequency characteristics. This approach combines ZOH and polynomial approximations to validate digital controllers for buck or boost converters.

How do I verify robust stability for a digital power electronics controller?▼

To verify robust stability for a digital power electronics controller, perform open-loop T(z) analysis to check phase margin and gain margin. This validates the controller against standard references while accounting for computational delay and ZOH effects.