dft

Automate DFT flows including scan insertion, ATPG, MBIST, and JTAG.

180|46|Updated Apr 12, 2026

Search Tags:#eda #dft #chip testability #test pattern generation #scan insertion

Ready to run

npx skills add https://github.com/chuanseng-ng/digital-chip-design-agents --skill dft

💬 Prompt for ChatGPT / Claude Chat▼

Please help me install this Agent Skill.
Skill: dft
Source: https://github.com/chuanseng-ng/digital-chip-design-agents/tree/main/plugins/dft/skills/dft
Command: npx skills add https://github.com/chuanseng-ng/digital-chip-design-agents --skill dft

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill requires yosys, openroad, tmax, modus, tessent, and includes scripts (resource) and references (resource) components.

What problem does it solve?

This Skill automates the Design for Test (DFT) process, from architecture planning to ATPG pattern generation, ensuring that chips are testable in manufacturing.

Core Features & Use Cases

DFT Architecture Planning: Guides the complete DFT flow from architecture planning through ATPG pattern generation, BIST insertion, JTAG setup, and sign-off.
Supported EDA Tools: Integrates with open-source and proprietary EDA tools like Yosys, OpenROAD, TetraMAX ATPG, Modus Test, and Tessent.
Use Case: Ideal for engineers who need to plan a DFT strategy, insert scan, generate test patterns, or verify chip testability.

Quick Start

Run the DFT skill to plan the DFT architecture for your design.

Frequently Asked Questions about dft

High-intent search queries and answers about installing and using this skill.

FAQPage Schema

How do I automate scan insertion and ATPG pattern generation for chip testability?▼

Automating scan insertion and ATPG pattern generation involves planning the DFT architecture, inserting scan chains, and generating test patterns using EDA tools like TetraMAX ATPG and Modus Test to ensure chip testability. This Skill orchestrates the complete flow from architecture planning through sign-off.

Does this DFT flow support both open-source and proprietary EDA tools?▼

Yes, the DFT flow supports both open-source and proprietary EDA tools. It integrates with Yosys and OpenROAD alongside industry-standard tools like TetraMAX ATPG, Modus Test, and Tessent to provide flexible chip testability analysis and pattern generation.

What is the best way to set up JTAG boundary scan and MBIST for embedded memories?▼

The best way to set up JTAG boundary scan and MBIST for embedded memories is to follow a structured DFT architecture plan. This Skill guides the complete flow, integrating BIST insertion and JTAG setup with tools like Tessent to verify chip testability.

Can I use Yosys and OpenROAD for DFT architecture planning and test pattern generation?▼

Yes, you can use Yosys and OpenROAD within this DFT flow. They are integrated alongside proprietary tools to support DFT architecture planning, scan insertion, and testability analysis, providing an open-source path for chip testability verification.

Why do I need Design for Test processes before manufacturing chips?▼

You need Design for Test processes to ensure chips are testable in manufacturing. Implementing DFT architecture planning, scan insertion, and ATPG pattern generation identifies manufacturing defects, verifying chip testability before production sign-off.