dft
CommunityAutomate Design for Test processes, ensure chip testability.
Authorchuanseng-ng
Version1.0.0
Installs0
System Documentation
What problem does it solve?
This Skill automates the Design for Test (DFT) process, from architecture planning to ATPG pattern generation, ensuring that chips are testable in manufacturing.
Core Features & Use Cases
- DFT Architecture Planning: Guides the complete DFT flow from architecture planning through ATPG pattern generation, BIST insertion, JTAG setup, and sign-off.
- Supported EDA Tools: Integrates with open-source and proprietary EDA tools like Yosys, OpenROAD, TetraMAX ATPG, Modus Test, and Tessent.
- Use Case: Ideal for engineers who need to plan a DFT strategy, insert scan, generate test patterns, or verify chip testability.
Quick Start
Run the DFT skill to plan the DFT architecture for your design.
Dependency Matrix
Required Modules
yosysopenroadtmaxmodustessent
Components
scriptsreferences
💻 Claude Code Installation
Recommended: Let Claude install automatically. Simply copy and paste the text below to Claude Code.
Please help me install this Skill: Name: dft Download link: https://github.com/chuanseng-ng/digital-chip-design-agents/archive/main.zip#dft Please download this .zip file, extract it, and install it in the .claude/skills/ directory.
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