skills.rest
KishoreDamam
KishoreDamamCOMMUNITY
Explore all skills by this author →
WebsiteGitHub

dft-patterns

Diagnose DFT insertion and ATPG coverage problems in VLSI RTL designs.

1|1|Updated Jan 29, 2026
Search Tags:#coverage#dft#jtag#atpg#scan chains#mbist#fault models
One-click install
npx skills add https://github.com/KishoreDamam/VLSI-agkit --skill dft-patterns
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: dft-patterns
Source: https://github.com/KishoreDamam/VLSI-agkit/tree/main/.agent/skills/dft-patterns
Command: npx skills add https://github.com/KishoreDamam/VLSI-agkit --skill dft-patterns

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve?

This Skill helps you design, review, and repair DFT testability issues so your ASIC can achieve sign-off-worthy scan and ATPG coverage.

Core Features & Use Cases

  • DFT methodology for scan, MBIST/LBIST, and JTAG/TAP: Apply correct design-for-test techniques when inserting scan chains, memory BIST, and boundary scan logic.
  • Coverage-focused fault model guidance: Evaluate stuck-at vs transition vs delay vs bridging, and interpret coverage vs untestable gaps without misleading reporting.
  • DFT DRC-oriented RTL fixes: Identify and remediate common blockers such as latch inference, gated clocks lacking test enable visibility, and async resets that can’t be bypassed in test mode.
  • Practical insertion flow: Turn DFT intent into tool-ready steps for scan configuration, DRC, insertion, and test protocol generation.

Quick Start

Use the dft-patterns skill to review your RTL for scan/ATPG blockers and produce a targeted DFT fix plan for scan chains, MBIST/LBIST, and JTAG/TAP coverage.

Frequently Asked Questions about dft-patterns

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I diagnose low ATPG coverage in my VLSI RTL design?▼

Diagnose low ATPG coverage by applying scan, MBIST/LBIST, and JTAG/TAP testability techniques to identify controllability and observability gaps, then interpreting untestable fault results to guide targeted RTL fixes and engineering change orders.

What is the best way to fix DFT DRC violations like latch inference and gated clocks?▼

Fix DFT DRC violations by enforcing DFT rules on non-scannable structures, ensuring test enable visibility for gated clocks, and modifying async resets so they can be bypassed during test mode to satisfy scan insertion requirements.

How do I choose the right fault model for achieving my ATPG coverage goals?▼

Choose the right fault model by evaluating stuck-at versus transition versus delay versus bridging faults, then mapping your specific ATPG coverage goals and untestable gaps to the appropriate fault class for accurate testability reporting.

What are the steps to insert scan chains and generate a test protocol for an ASIC?▼

Steps to insert scan chains include configuring scan architecture, running DRC to validate testability, inserting scan logic, and generating test protocols by turning DFT intent into tool-ready steps for scan configuration and test protocol generation.

Why does my scan chain insertion fail on non-scannable structures during DFT?▼

Scan chain insertion fails when RTL contains non-scannable structures like latches or async resets lacking test mode bypasses, requiring you to enforce DFT rules and remediate testability blockers before successful scan insertion.

Related Skills

Explore More Software Engineering Skills→
KishoreDamamKishoreDamam
1

synopsys-flow

Orchestrate Synopsys ASIC front-end steps from RTL synthesis to formal verification.

Community
Advanced
LNC0831LNC0831
11

coverage-closure

Orchestrate RTL simulation coverage closure for FPGA designs.

Community
Advanced
chuanseng-ngchuanseng-ng
180

dft

Automate DFT flows including scan insertion, ATPG, MBIST, and JTAG.

Community
Advanced
babywormbabyworm
43

systemverilog-assertion

Generate SystemVerilog assertion bind files with naming, clock/reset guards, and sv2v guidance.

Community
Advanced