dft-patterns

What problem does it solve?

This Skill helps you design, review, and repair DFT testability issues so your ASIC can achieve sign-off-worthy scan and ATPG coverage.

Core Features & Use Cases

• DFT methodology for scan, MBIST/LBIST, and JTAG/TAP: Apply correct design-for-test techniques when inserting scan chains, memory BIST, and boundary scan logic.
• Coverage-focused fault model guidance: Evaluate stuck-at vs transition vs delay vs bridging, and interpret coverage vs untestable gaps without misleading reporting.
• DFT DRC-oriented RTL fixes: Identify and remediate common blockers such as latch inference, gated clocks lacking test enable visibility, and async resets that can’t be bypassed in test mode.
• Practical insertion flow: Turn DFT intent into tool-ready steps for scan configuration, DRC, insertion, and test protocol generation.

Quick Start

Use the dft-patterns skill to review your RTL for scan/ATPG blockers and produce a targeted DFT fix plan for scan chains, MBIST/LBIST, and JTAG/TAP coverage.