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dit-parallel-opt

Selects and validates multi-card parallelism strategies for DiT inference on Ascend NPUs.

14|5|Updated Mar 30, 2026
Search Tags:#distributed#parallelism#hccl#ascend npu#communication masking#ulysses#dit inference
One-click install
npx skills add https://github.com/Ascend/MindIE-SD --skill dit-parallel-opt-ascend
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: dit-parallel-opt
Source: https://github.com/Ascend/MindIE-SD/tree/main/.agents/skills/dit-parallel-opt
Command: npx skills add https://github.com/Ascend/MindIE-SD --skill dit-parallel-opt-ascend

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes scripts (resource) and references (resource) components.

What problem does it solve? Choosing and verifying distributed parallelism for diffusion transformer (DiT) inference is error-prone: Ulysses/CP/TP/RSP/PP forms behave differently across interconnect topologies, communication masking often fails silently, and few-step benchmarks can produce rankings that do not extrapolate to full-step runs. This Skill provides tested selection criteria, masking upper-bound analysis, and diagnostic protocols for multi-card Ascend NPU deployments. ## Core Features & Use Cases - Parallelism strategy selection: Compares USP, CFG, TP, RSP, PP and composite AllGather-KV × Ulysses forms with topology-aware rules (same-domain bulk vs cross-domain head-parallel) and a seven-gate decision flow including GQA and communication lower bounds. - Communication masking analysis: Computes the true masking ceiling from per-layer C/F ratios (when 1-1/n is unreachable), provides implementation recipes (chunked pipelining, block-level events, single active communicator), and verifies effectiveness via operator counts, side-stream AI-core checks, and byte-identical outputs. - Few-step multi-rank validation protocol: Defines a DiT-only timing methodology with dispersion gates (3%) and drift thresholds (5%) to decide whether few-step rankings extrapolate to full-step runs. - Failure diagnosis: Covers HcclAlltoAllV SIGSEGV workarounds, silent sequence-parallel deactivation, port-bind errors, CP × sparse-attention seam contracts, and parallel-plan attribution via stage-delta decomposition and collective grouping. - Use Case: When profiling shows 30% exposed communication on an 8-card run, use the masking bound calculator to determine whether the ceiling is the limiting factor, then apply the chunked pipelining recipe and verify with the provided attribution scripts. ## Quick Start Ask the assistant to help choose between pure Ulysses and composite AllGather-KV parallelism for your multi-card DiT deployment, or to diagnose why communication masking is not reaching its expected ratio.

Frequently Asked Questions about dit-parallel-opt

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I choose between Ulysses and composite AllGather-KV parallelism?▼

Compare per-rank per-layer total bytes across cross-island versus same-island links rather than which collective is faster. GQA is the first gating variable: without GQA both forms move nearly identical cross-island bytes, so the composite form has no communication advantage and its extra compute plumbing usually makes it slower.

Why is my communication masking rate below the theoretical 1-1/n bound?▼

The 1-1/n bound only holds when per-chunk compute f >= per-chunk communication c. When c/f > 1 the real ceiling degrades to 1-(c+(n-1)(c-f)+drain)/C and adding more chunks does not help; the fix is shrinking the communication payload via quantization, reducing cross-island traffic, or merging collectives.

Can few-step benchmarks predict full-step parallelism rankings?▼

Yes, but only with gates: use DiT-only timing excluding VAE decode and warmup, require per-cell dispersion under 3%, per-step drift |r-1| under 5%, and consistent ranking between few-step and anchor tiers. Any ranking flip means the anchor tier wins and few-step results are discarded.

Why does HcclAlltoAllV crash with SIGSEGV on Ascend?▼

Some CANN versions have a defect in the HcclAlltoAllV split path while equal-split HcclAlltoAll works. The workaround pads inputs to a 128-multiple S_PAD, exchanges with equal-split HcclAlltoAll, then slices; verify success by checking the kernel name changes from hcom_alltoallv to hcom_alltoall.

Why does CP plus sparse attention produce byte-identical output to the dense baseline?▼

Byte-identical output means sparsity never took effect, not that it is lossless. Some parallel paths bypass the attention backend entirely, silently dropping sparsity; treat this as a failed activation and never count it toward combination gains.

How do I fix 'port already been bound' errors in HCCL torchrun microbenchmarks?▼

Call torch_npu.npu.set_device(local_rank) before init_process_group; without it every rank binds the same port. This is not a port leak, though genuine leaks from SIGKILLed jobs require switching card groups or a driver reset.

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