Automate design space exploration by iteratively running programs and tuning parameters.
npx skills add https://github.com/dogekiki/SP-test --skill dse-loop-dogekiki
Please help me install this Agent Skill. Skill: dse-loop Source: https://github.com/dogekiki/SP-test/tree/main/.trae/skills/dse-loop Command: npx skills add https://github.com/dogekiki/SP-test --skill dse-loop-dogekiki
This skill automates the iterative process of tuning parameters in complex engineering workflows, such as computer architecture simulations or EDA toolchains, to find the optimal configuration without manual intervention.
Use the dse-loop skill to run the gem5 simulation and tune the cache size and pipeline width to maximize IPC with a 2 hour timeout.
High-intent search queries and answers about installing and using this skill.
Automating parameter tuning for computer architecture simulations involves iteratively running programs, analyzing extracted metrics, and adjusting parameters to find the optimal configuration without manual intervention.
Autonomous design space exploration for EDA automatically iterates through toolchain configurations to optimize results like area or timing closure based on defined objective functions and constraints.
Yes, you can optimize gem5 simulation parameters like cache size and pipeline width to maximize IPC by applying an autonomous loop that infers parameter ranges and tunes them until a timeout occurs.
To tune yosys synthesis scripts to minimize area at timing closure, apply an iterative parameter sweep that analyzes synthesis results and adjusts configurations to meet defined objective functions and constraints.
To run formal verification parameter sweeps autonomously, you need programmatic metric extraction, defined objective functions, and specified constraints to guide the iterative tuning process.
The system infers parameter ranges for performance optimization by analyzing source code directly and applying domain-specific strategies to explore the design space efficiently.
loujcAutomates iterative design-space exploration for software/hardware optimization.
TabithaFannyAutomate design space exploration by running simulations and tuning parameters.
chuanseng-ngAutomate ASIC RTL adaptation, synthesis, and bring-up for FPGA prototypes.
shuff57Fine-tunes large language models with LoRA and QLoRA for constrained GPU memory.
