dse-loop

Automated design space exploration runs a program, analyzes outputs, and iteratively tunes architecture parameters until an objective is met or a timeout occurs, reducing manual trial-and-error workflows.

Iterative parameter tuning in EDA autonomously explores synthesis configurations by running design points, logging results, and adjusting parameters across iterations to converge on optimum performance.

RTL parameterization workflows support configurable time budgets and iteration limits, allowing you to constrain long-running experiments and automatically halt when the exploration objective is met.

Long-running formal verification experiments maintain state recovery and result logging capabilities within a designated directory, ensuring reproducibility and allowing interrupted optimization workflows to resume.

Design space exploration requires a baseline configuration as a starting point, enabling the loop to generate initial results and systematically evaluate parameter variations against that baseline.

Automating parameter inferences for processor configurations is bounded by configured time budgets and iteration limits, meaning complex design spaces may require multiple runs or manual adjustments to fully converge.