dse-loop

Automate parameter tuning for computer architecture simulation sweeps by iteratively running the target workload, parsing the output for a numeric objective metric, and guiding subsequent parameter choices. This applies to simulation scripts, synthesis tuning, and formal verification settings.

Yes, you can optimize EDA synthesis and routing flows without manual ranges because the system reads the source code to infer valid parameter types and sensible sweep values when missing. It logs the inferred design space for your review before proceeding.

The design space exploration loop stops running iterations based on predefined timeout limits, maximum iteration counts, patience thresholds, and success criteria. It records run outputs and recovery state in JSON to ensure deterministic logging throughout the process.

The best way to tune RTL verification parameters is to set a target metric and let the autonomous run-analyze-iterate loop execute. It extracts the metric from each run, adjusts inputs accordingly, and stops automatically when the target is reached or time expires.

No, you do not need to manually log outputs when running gem5 or Yosys parameter optimization. The system creates a full run directory with CSV logs, output files, state recovery JSON, and a final markdown report with convergence details and recommendations.

When inferring valid parameter types from source code for EDA optimization, the limitation is that the inferred design space must be reviewed to ensure the sensible sweep values match your constraints before the autonomous iteration begins.