dv-sequences

What problem does it solve?

DV end-to-end design verification often requires manually creating and wiring UVM sequences, virtual sequences, and test classes from a DV testplan and an existing testbench. This skill automates that workflow by producing production-ready SystemVerilog components that plug into the DV flow.

Core Features & Use Cases

• Generate UVM sequences and tests from a DV testplan (Excel or JSON) and an existing UVM testbench.
• Create directed test sequences for specific testplan rows and generate randomized virtual sequences for coverage-driven tests.
• Generate per-VIP protocol sequences (write, read, burst, error injection) and UVM test classes with plusargs, cfg constraints, and vseq execution.
• Generate a single testcase interactively from a natural-language description and run /dv-sequences or S6 in the DV end-to-end flow.

Quick Start

Provide a DV testplan (Excel or JSON) and a dv_tb_data.json, then run the S6 workflow to generate sequences and tests.