Generate UVM sequences, virtual sequences, and test classes from a DV testplan.
npx skills add https://github.com/rajivhasija79-bit/DV-Skills --skill dv-sequences
Please help me install this Agent Skill. Skill: dv-sequences Source: https://github.com/rajivhasija79-bit/DV-Skills/tree/main/skills/dv-sequences Command: npx skills add https://github.com/rajivhasija79-bit/DV-Skills --skill dv-sequences
DV end-to-end design verification often requires manually creating and wiring UVM sequences, virtual sequences, and test classes from a DV testplan and an existing testbench. This skill automates that workflow by producing production-ready SystemVerilog components that plug into the DV flow.
Provide a DV testplan (Excel or JSON) and a dv_tb_data.json, then run the S6 workflow to generate sequences and tests.
High-intent search queries and answers about installing and using this skill.
You can generate randomized virtual sequences by supplying a DV testplan and an existing UVM testbench description. The skill automates coverage-driven test creation by producing randomized virtual sequences that integrate with your testbench environment.
Yes, you can create directed test sequences for specific testplan rows. The skill automates translating individual testplan entries into directed SystemVerilog UVM sequences, allowing precise scenario targeting within your design verification workflow.
Yes, the skill generates per-VIP protocol sequences including write, read, burst, and error injection scenarios. It creates these protocol-specific UVM sequences alongside UVM test classes configured with plusargs and cfg constraints.
Yes, you can generate a single test case interactively from a natural-language description. The skill processes your description to produce the corresponding UVM sequence and test class within the design verification end-to-end flow.
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KishoreDamamImplement UVM 1.2 SystemVerilog testbench coding patterns for sequences, drivers, and scoreboards.
