dv-tb-scaffold

What problem does it solve?

dv-tb-scaffold automates the creation of a complete, production-grade UVM DV testbench scaffold from a DUT specification. It identifies unique VIP protocols in the DUT interface list, generates fully parameterized VIP components (driver, monitor, sequencer, sequence item, config, agent, functional coverage, base sequences), creates a UVM RAL model from a register map, builds the top-level environment (env, env_cfg, scoreboard, reference model, virtual sequencer), and produces a DUT RTL stub ready for immediate compilation in SystemVerilog/UVM.

Core Features & Use Cases

• Generate a complete UVM testbench scaffold from a DUT spec or outputs (S1/S2/S3/S4).
• Create VIPs (agent/driver/monitor/sequencer/coverage) for AXI/AHB/APB/SPI/I2C/UART or proprietary protocols.
• Generate a UVM RAL model from a register map.
• Create a DUT RTL stub for testbench bring-up.
• Set up the full UVM env hierarchy (env, scoreboard, ref model, virtual sequencer).
• Run the full S5 flow to produce ready-to-use DV scaffolds.

Quick Start

Provide the DUT interface list and register map (or run the S5 flow) to generate a complete DV testbench scaffold.