dv-tb-scaffold

Generate a complete UVM DV testbench scaffold from a DUT specification.

3|4|Updated Mar 21, 2026
One-click install
npx skills add https://github.com/rajivhasija79-bit/DV-Skills --skill dv-tb-scaffold
Or copy as Structured Prompt for Agent
Please help me install this Agent Skill.
Skill: dv-tb-scaffold
Source: https://github.com/rajivhasija79-bit/DV-Skills/tree/main/skills/dv-tb-scaffold
Command: npx skills add https://github.com/rajivhasija79-bit/DV-Skills --skill dv-tb-scaffold

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

dv-tb-scaffold automates the creation of a complete, production-grade UVM DV testbench scaffold from a DUT specification. It identifies unique VIP protocols in the DUT interface list, generates fully parameterized VIP components (driver, monitor, sequencer, sequence item, config, agent, functional coverage, base sequences), creates a UVM RAL model from a register map, builds the top-level environment (env, env_cfg, scoreboard, reference model, virtual sequencer), and produces a DUT RTL stub ready for immediate compilation in SystemVerilog/UVM.

Core Features & Use Cases

  • Generate a complete UVM testbench scaffold from a DUT spec or outputs (S1/S2/S3/S4).
  • Create VIPs (agent/driver/monitor/sequencer/coverage) for AXI/AHB/APB/SPI/I2C/UART or proprietary protocols.
  • Generate a UVM RAL model from a register map.
  • Create a DUT RTL stub for testbench bring-up.
  • Set up the full UVM env hierarchy (env, scoreboard, ref model, virtual sequencer).
  • Run the full S5 flow to produce ready-to-use DV scaffolds.

Quick Start

Provide the DUT interface list and register map (or run the S5 flow) to generate a complete DV testbench scaffold.

Frequently Asked Questions about dv-tb-scaffold

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I auto-generate a UVM testbench from a DUT specification?

You can auto-generate a complete UVM testbench by providing a DUT interface list and register map, which produces parameterized VIPs, a RAL model, and a ready-to-run dv/ directory.

What VIP protocols are supported when scaffolding a SystemVerilog DV environment?

Scaffolding a SystemVerilog DV environment supports AXI, AHB, APB, SPI, I2C, UART, TileLink, and proprietary protocols by generating fully parameterized VIP components like drivers, monitors, and sequencers.

Can I generate a UVM RAL model and DUT stub from a register map?

Yes, you can generate a UVM RAL model from a register map and a DUT RTL stub for immediate compilation, allowing rapid testbench bring-up before the actual RTL is fully available.

Does the generated UVM environment include a scoreboard and reference model?

Yes, the generated UVM environment includes the full hierarchy: an environment configuration, scoreboard, reference model, and virtual sequencer, creating a production-grade testbench scaffold.

What inputs are required to scaffold a complete UVM DV testbench?

You need a DUT interface list and a register map, or alternatively the S1/S2/S3/S4 flow outputs, to scaffold the complete UVM DV testbench and generate the dv_tb_data.json artifact.