ee-power-integrity

Name: ee-power-integrity
Availability: InStock
Author: 6987zshmpy-bot

Calculate PDN target impedance and plan tiered decoupling networks for multi-rail designs.

Updated Aug 23, 2026

Search Tags:#decoupling #pdn #layout-verification #power-integrity #target-impedance #multirail

Ready to run

npx skills add https://github.com/6987zshmpy-bot/electrical-engineering-plugin --skill ee-power-integrity

💬 Prompt for ChatGPT / Claude Chat▼

Please help me install this Agent Skill.
Skill: ee-power-integrity
Source: https://github.com/6987zshmpy-bot/electrical-engineering-plugin/tree/main/skills/ee-power-integrity
Command: npx skills add https://github.com/6987zshmpy-bot/electrical-engineering-plugin --skill ee-power-integrity

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve?

Power engineers often struggle to design robust multi-rail power delivery systems, and this skill provides a structured approach to PDN design by guiding target impedance calculations and decoupling network planning.

Core Features & Use Cases

Inventory all rails and transient requirements to establish a design scope.
Calculate per-rail target impedance and design a tiered decoupling network to meet it.
Verify layout considerations and produce a PDN design report for documentation and review.

Quick Start

List the rails, voltages, and transient specs, then run a PDN design pass to generate a target impedance and decoupling plan.

Frequently Asked Questions about ee-power-integrity

High-intent search queries and answers about installing and using this skill.

FAQPage Schema

How do I calculate PDN target impedance for multi-rail designs?▼

To calculate PDN target impedance for multi-rail designs, inventory all rails, voltages, and transient specs. The skill evaluates transient demands per rail to establish target impedance and generate a tiered decoupling plan.

What is tiered decoupling network design and when do I need it?▼

Tiered decoupling network design arranges capacitors to meet target impedance across frequencies. You need it when designing robust power delivery for multi-rail systems like MCUs, analog references, and FPGAs to handle transient currents.

How do I plan decoupling networks for FPGAs and multi-rail MCUs?▼

Plan decoupling networks for FPGAs and multi-rail MCUs by listing each rail's voltage and transient requirements. The design pass evaluates these transient demands to produce a tiered decoupling layout and verification report.

Can I generate a formal power integrity layout verification report?▼

Yes, you can generate a formal layout verification report. After calculating target impedance and planning the decoupling network, the skill verifies layout considerations and produces a PDN design report for documentation and review.

What's the best way to evaluate transient demands for analog reference rails?▼

The best way to evaluate transient demands for analog reference rails is establishing a design scope by inventorying all rails and transient specs, then calculating per-rail target impedance to guide the decoupling network design.