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JasonYANG170
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esp-sr-skill

Generate ESP-SR offline speech recognition firmware code for ESP32 chips using verified APIs.

28|3|Updated Jun 24, 2026
Search Tags:#speech recognition#embedded#esp32#esp-idf#wake word#voice commands#esp-sr
One-click install
npx skills add https://github.com/JasonYANG170/esp-dev-skill --skill esp-sr-skill-jasonyang170
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: esp-sr-skill
Source: https://github.com/JasonYANG170/esp-dev-skill/tree/main/repos/esp-sr
Command: npx skills add https://github.com/JasonYANG170/esp-dev-skill --skill esp-sr-skill-jasonyang170

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve? Developing offline voice applications with Espressif ESP-SR requires navigating version-specific APIs (V1 vs V2), model partition configuration, AFE pipeline setup, and numerous pitfalls like misaligned buffers or missing command updates. This Skill grounds all generated code in the real esp-sr repository headers, docs, and test_apps so the AI never invents nonexistent interfaces. ## Core Features & Use Cases - Scenario Recipes: Step-by-step guides for the AFE speech recognition pipeline (WakeNet + MultiNet), model partition flashing, V1-to-V2 migration, standalone WakeNet, custom Chinese/English command words, VADNet, AEC echo cancellation, DOA sound localization, VC/full-duplex pipelines, and Chinese TTS. - Verified API & Config Reference: Complete function signatures, structs, enums, Kconfig symbols, threshold ranges, and chip/model support matrices extracted from the actual repository. - Pitfall Prevention: 20 documented mistakes with WRONG/CORRECT code pairs, such as deprecated AFE_CONFIG_DEFAULT usage, missing esp_mn_commands_update(), and unaligned AEC buffers. - Use Case: Ask the AI to build a wake-word plus command-word project on ESP32-S3; it produces the partition table, menuconfig model selection, feed/fetch dual-task code, and build commands that compile against ESP-IDF >= 5.0. ## Quick Start Ask the AI to create an ESP-SR voice recognition project on ESP32-S3 with a wake word and two Chinese command words, including the partition table and build steps.

Frequently Asked Questions about esp-sr-skill

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I build a wake word and command word project with ESP-SR?▼

Use the AFE speech recognition pipeline: add a model partition to partitions.csv, select WakeNet and MultiNet models in menuconfig, initialize with afe_config_init and esp_afe_handle_from_config, then run feed and fetch tasks. After WAKENET_DETECTED, feed fetch results into multinet->detect().

How do I migrate ESP-SR V1 code to V2.0?▼

Replace the removed AFE_CONFIG_DEFAULT and ESP_AFE_SR_HANDLE macros with afe_config_init(input_format, models, type, mode) and esp_afe_handle_from_config(). Load models via esp_srmodel_init("model") and create instances with create_from_config().

Which ESP chips support ESP-SR WakeNet and MultiNet?▼

WakeNet runs on ESP32, S2, S3, S31, P4, C3, C5, and C6, but C-series chips without PSRAM or SIMD must use the wn9s model variants. MultiNet Chinese and English models require ESP32, S3, S31, or P4; C-series chips do not support MultiNet.

Why are my custom MultiNet command words not recognized?▼

Commands added with esp_mn_commands_add only take effect after calling esp_mn_commands_update(), which must return NULL. Commands cannot contain digits or special characters, Chinese uses pinyin for mn6/mn7, and English mn5 requires phoneme strings from the multinet_g2p.py tool.

Why does ESP-SR AEC crash or fail to remove echo?▼

AEC crashes when mic, ref, or output buffers are not 16-byte aligned; allocate them with heap_caps_aligned_alloc(16, ...). If echo remains, switch from SR mode to FD mode or raise the NLP level to AEC_NLP_LEVEL_VERYAGGR.

When should I not use ESP-SR for speech recognition?▼

ESP-SR is unsuitable for cloud-based ASR or large-model voice dialogue since it is a purely offline embedded solution. It also does not cover non-Espressif chips, and WakeNet9 high-performance models cannot run on chips without PSRAM and SIMD support.

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