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esp32p4-simd

Converts scalar code into ESP32-P4 PIE SIMD assembly for neural network operators.

1.1k|222|Updated Nov 16, 2018
Search Tags:#vectorization#simd#assembly#esp-dl#esp32-p4#pie instructions#neural network operators
One-click install
npx skills add https://github.com/espressif/esp-dl --skill esp32p4-simd
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: esp32p4-simd
Source: https://github.com/espressif/esp-dl/tree/main/tools/agents/skills/esp32p4-pie-simd
Command: npx skills add https://github.com/espressif/esp-dl --skill esp32p4-simd

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve?

Writing high-performance neural network operators for the ESP32-P4 requires deep knowledge of its custom PIE SIMD instruction set, register architecture, and accumulator semantics, which is error-prone and slow to do from scratch.

Core Features & Use Cases

  • Complete PIE Instruction Reference: Covers read/write, data exchange, arithmetic, comparison, bitwise, shift, and FFT-dedicated instructions operating on 128-bit QR vector registers with QACC/XACC accumulators.
  • Scalar-to-SIMD Conversion Workflow: Provides a step-by-step optimization process covering alignment handling, SAR shift configuration, fused load-arithmetic instructions, and remainder processing.
  • Production Code Patterns: Includes real esp-dl assembly examples for conv2d, depthwise convolution, elementwise add, GEMM dot products, pooling, and ReLU/PReLU activations.
  • Use Case: When implementing a new int16 convolution kernel for esp-dl on ESP32-P4, use this Skill to generate the assembly loop using vsmulas.s16.qacc MAC instructions with proper bias loading, shift extraction, and label conventions.

Quick Start

Rewrite this scalar int16 elementwise add function as an ESP32-P4 PIE SIMD assembly implementation following the esp-dl patterns.

Frequently Asked Questions about esp32p4-simd

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I convert scalar code to ESP32-P4 SIMD assembly?▼

Follow the optimization workflow: check data alignment, set the SAR register before multiply instructions, process data in 128-bit chunks, use fused load-arithmetic instructions like esp.vadd.s16.ld.incp, accumulate with QACC/XACC, and handle tail elements separately.

What vector registers does the ESP32-P4 PIE extension provide?▼

The PIE extension provides eight 128-bit QR registers (q0-q7), each holding 16 x 8-bit, 8 x 16-bit, or 4 x 32-bit elements. It also includes 256-bit QACC_H/L accumulators and a 40-bit XACC accumulator for dot products.

How do I handle unaligned memory access in ESP32-P4 SIMD code?▼

Use esp.ld.128.usar.ip to load unaligned data, which sets SAR_BYTE from the address LSBs, then combine two consecutive loads with esp.src.q to extract properly aligned 128-bit data. Alternatively enable hardware misaligned handling via the CFG register mis_ld/mis_st bits.

Which instructions implement multiply-accumulate for conv2d on ESP32-P4?▼

Use esp.vmulas.s16.qacc for vector-vector MAC into QACC, or esp.vsmulas.s16.qacc for scalar-vector MAC where one element is selected from a register. Extract results with esp.srcmb.s16.qacc after setting the SAR shift amount.

What label naming convention is required for PIE assembly loops?▼

Use local labels only: numeric labels like 0: referenced as 0f/0b, or .L-prefixed names like .Lloop. Full descriptive global-style labels such as loop_start: are not allowed because they pollute the symbol table and risk name clashes.

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