What problem does it solve? Optimizing AscendC kernels for Ascend NPU hardware requires deep knowledge of hardware architecture, API pitfalls, and proven optimization patterns that is scattered and hard to recall during iterative kernel evolution workflows. ## Core Features & Use Cases - Hardware Architecture Reference: Documents Ascend 910B specifics including UB size, core counts, pipeline models, DMA efficiency thresholds, and Roofline analysis for bottleneck diagnosis. - Optimization Pattern Library: Provides code templates with measured impact ranges for double buffering, tiling strategies, causal block skipping, pipeline overlap, memory coalescing, and scalar-to-vector conversion. - API Pitfall Catalog: Lists the top 15+ common AscendC coding mistakes (alignment violations, EnQue/DeQue mismatches, tail block handling) with symptom-to-fix lookup tables. - Use Case: When an evolution agent needs to optimize a memory-bound reduction kernel, it reads the hardware guide and optimization patterns guide, then applies double buffering and scalar-to-vector conversion patterns with the documented code templates. ## Quick Start Query the knowledge base by reading the guide.md file in the category matching your current optimization stage, such as references/a3/optimization_patterns/guide.md before writing kernel code.
