fast-elaborator

What problem does it solve?

This Skill provides rapid Power, Performance, and Area (PPA) analysis for RTL designs without requiring a full Electronic Design Automation (EDA) flow.

Core Features & Use Cases

• Quick Synthesis: Synthesizes RTL designs using Yosys for immediate analysis.
• PPA Estimation: Offers gate counts, flip-flop counts, and logic depth analysis.
• Hierarchy Navigation: Allows exploration of the design's hierarchical structure.
• Use Case: Quickly estimate the gate count and critical path logic depth of a Verilog module before committing to a lengthy synthesis run.

Quick Start

Load the design file 'design.v' with 'my_module' as the top-level module.