fexpand

What problem does it solve?

This Skill preprocesses and flattens hierarchical Verilog/SystemVerilog filelists, resolving includes, environment variables, and macros into a single, clean filelist.

Core Features & Use Cases

• Hierarchical Filelist Expansion: Flattens nested .f files into a single list.
• Environment Variable Resolution: Expands $VAR and ${VAR} references.
• Macro Preprocessing: Handles `ifdef/`endif and #ifdef/endif directives.
• Path Deduplication: Removes duplicate file entries.
• VHDL File Splitting: Separates .vhd/.vhdl files into a distinct output.
• Use Case: When dealing with complex FPGA or ASIC projects that use multiple Verilog/SystemVerilog filelists, this Skill ensures a unified and correctly processed list of all source files for simulation or synthesis.

Quick Start

Use the fexpand skill to flatten the input filelist 'top.f' into 'flat.f' with the 'SYNTHESIS' macro defined.