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fexpand

Flatten hierarchical Verilog/SystemVerilog filelists using the fexpand CLI tool.

1|1|Updated Jun 15, 2023
Search Tags:#preprocessing#eda#systemverilog#verilog#filelist#fexpand
One-click install
npx skills add https://github.com/Paradicat/demo --skill fexpand
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: fexpand
Source: https://github.com/Paradicat/demo/tree/main/agent_pack/skills/fexpand
Command: npx skills add https://github.com/Paradicat/demo --skill fexpand

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve?

This Skill preprocesses and flattens hierarchical Verilog/SystemVerilog filelists, resolving includes, environment variables, and macros into a single, clean filelist.

Core Features & Use Cases

  • Hierarchical Filelist Expansion: Flattens nested .f files into a single list.
  • Environment Variable Resolution: Expands $VAR and ${VAR} references.
  • Macro Preprocessing: Handles `ifdef/`endif and #ifdef/endif directives.
  • Path Deduplication: Removes duplicate file entries.
  • VHDL File Splitting: Separates .vhd/.vhdl files into a distinct output.
  • Use Case: When dealing with complex FPGA or ASIC projects that use multiple Verilog/SystemVerilog filelists, this Skill ensures a unified and correctly processed list of all source files for simulation or synthesis.

Quick Start

Use the fexpand skill to flatten the input filelist 'top.f' into 'flat.f' with the 'SYNTHESIS' macro defined.

Frequently Asked Questions about fexpand

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I flatten a hierarchical Verilog filelist into a single list?▼

Flatten hierarchical Verilog filelists by expanding nested `.f` files, resolving includes, and deduplicating paths into a single, clean output filelist ready for simulation or synthesis.

What is the best way to resolve environment variables and macros in SystemVerilog filelists?▼

Resolve environment variables and macros in SystemVerilog filelists by expanding `$VAR` and `${VAR}` references alongside C99 and Verilog `ifdef/endif` directives during the filelist flattening process.

Can I separate VHDL files from Verilog files when expanding filelists?▼

Yes, you can separate VHDL files from Verilog files during filelist expansion by splitting `.vhd` and `.vhdl` entries into a distinct output list while processing the SystemVerilog sources.

How does path deduplication work when expanding nested Verilog filelists?▼

Path deduplication removes duplicate file entries when expanding nested Verilog filelists, ensuring the final flat list contains unique absolute paths for each source file without redundant includes.

Does fexpand support EDA directive passthrough during filelist preprocessing?▼

Yes, fexpand supports EDA directive passthrough during filelist preprocessing, allowing synthesis and simulation tool directives to pass directly into the flattened output without modification.

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