What problem does it solve? Training and fine-tuning runs on AMD Instinct GPUs (gfx942/gfx950) often bottleneck on attention backward kernels when the vendor fast path cannot dispatch natively — for example when head dims are asymmetric (hdim_q != hdim_v) and the tuned asm/CK backward pads or falls back to a slow generic path. This Skill provides a regulated, step-by-step procedure for authoring a fused multi-GEMM FlyDSL backward kernel that avoids padding overhead and register spills. ## Core Features & Use Cases - Structural kernel design guidance: Prescribes four key decisions — fusing all GEMMs into one kernel, operand-swapped MFMA fragment orientation, KV-outer looping to avoid atomics, and wave-count selection against the 256 arch-VGPR register cap. - Gated bring-up procedure: Enforces a dependency-ordered ladder (fp32 reference, harness with ISA probe, preprocess kernel, main kernel, incremental optimization, head-to-head benchmark) with parity gates of cos >= 0.999 on every gradient. - Documented dead ends: Lists measured anti-patterns (oversized KV tiles, dQ atomic fan-out, barrier folding) so engineers do not re-derive failed optimizations. - Use Case: An MLA attention backward with HD_QK=192/HD_V=128 on gfx942 reaches 1.38x speedup per unit of useful work versus the padded-ASM baseline by following this recipe. ## Quick Start Ask the agent to author a fused FlyDSL attention backward kernel for your asymmetric-head-dim training workload on gfx942, following the gated bring-up procedure with fp32 parity validation.
