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FlyDSL Tile Programming

Generate and validate FlyDSL GPU kernels from kernel specifications using tile programming.

260|104|Updated Nov 23, 2025
Search Tags:#gpu kernels#mma#flydsl#tile programming#layout algebra#cuTe#kernel generation
One-click install
npx skills add https://github.com/ROCm/FlyDSL --skill flydsl-tile-programming
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: FlyDSL Tile Programming
Source: https://github.com/ROCm/FlyDSL/tree/main/.claude/skills/flydsl-tile-programming
Command: npx skills add https://github.com/ROCm/FlyDSL --skill flydsl-tile-programming

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

FlyDSL Tile Programming solves the challenge of writing correct, efficient GPU kernels by guiding users through a CuTe-style tile programming workflow. It turns kernel requirements into a tested FlyDSL kernel via a step-by-step wizard.

Core Features & Use Cases

  • Classify the kernel pattern (Elementwise, Reduction, Tiled Copy, GEMM, Fused) and generate the appropriate skeleton.
  • Provide compute recipes, tile division, per-thread partitioning, and synchronization patterns for production-ready kernels.
  • Support porting Triton kernels and learning tile programming patterns for a range of GPU architectures and backends.

Quick Start

Start the FlyDSL Tile Programming wizard with a kernel requirement and let it produce a tested FlyDSL kernel.

Frequently Asked Questions about FlyDSL Tile Programming

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I write GPU kernels using tile programming and layout algebra?▼

GPU kernels using tile programming and layout algebra are generated and validated by classifying kernel patterns like elementwise or GEMM, then applying block-level tiling and per-thread partitioning to produce tested FlyDSL code.

How do I port Triton kernels to a CuTe-style tile programming workflow?▼

Porting Triton kernels to a CuTe-style tile programming workflow involves translating existing kernel specifications into FlyDSL, mapping compute recipes to block-level tiling and synchronization patterns for GPU deployment.

Can I generate fused GPU kernels for multiple operations using FlyDSL?▼

Yes, fused GPU kernels are supported by classifying the target pattern as fused, which generates a skeleton applying tile division, per-thread partitioning, and synchronization to produce a tested FlyDSL kernel.

Does FlyDSL tile programming support tiled copy and GEMM kernel generation?▼

Tiled copy and GEMM kernel generation are supported by classifying the specific kernel pattern, providing compute recipes and block-level tiling, and validating the resulting FlyDSL kernel for production readiness.

What is the best way to validate FlyDSL GPU kernels for different architectures?▼

Validating FlyDSL GPU kernels is handled through a testing workflow that checks block-level tiling, per-thread partitions, and synchronization patterns to ensure correct GPU deployment across architectures and backends.

Why do I need layout algebra and per-thread partitioning for GPU kernel generation?▼

Layout algebra and per-thread partitioning are required to correctly divide tiles and map compute recipes to threads, ensuring the generated FlyDSL GPU kernel satisfies synchronization and block-level tiling constraints.

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