foc-drive-embedded-c

Generate and review STM32G4 Field-Oriented Control firmware for PMSM/BLDC motor drives.

Updated Apr 27, 2026
One-click install
npx skills add https://github.com/KunYi/Skills --skill foc-drive-embedded-c
Or copy as Structured Prompt for Agent
Please help me install this Agent Skill.
Skill: foc-drive-embedded-c
Source: https://github.com/KunYi/Skills/tree/main/foc-embedded-c
Command: npx skills add https://github.com/KunYi/Skills --skill foc-drive-embedded-c

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve?

This Skill prevents broken or unsafe Field-Oriented Control implementations by enforcing physically verifiable, timing-aware guidance for STM32G4-class PMSM/BLDC motor drive firmware rather than generic FOC templates.

Core Features & Use Cases

  • Production-grade control architecture: guides inner current-loop determinism, cascaded speed/position logic, and safe transition sequencing.
  • Hardware-tied modulation and sensing: aligns SVPWM/SVPWM variants, ADC/DMA timing, shunt topology constraints, and STM32G4 PWM/trigger specifics.
  • Safety boundaries and emergency behavior: prioritizes OCP and DC-bus overvoltage handling with explicit safe-state selection (High-Z vs ASC), plus fault/abuse-case readiness.

Quick Start

Use the foc-drive-embedded-c skill to help you write or review STM32G4 FOC code for a PMSM using dual-ADC current sensing by asking for the required ISR pipeline, ADC trigger placement, SVPWM limits, and an emergency protection plan.

Frequently Asked Questions about foc-drive-embedded-c

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I implement FOC control for a PMSM using STM32G4?

Implementing FOC control for a PMSM on the STM32G4 requires a cascaded speed and position loop, SVPWM modulation, and deterministic current sensing. This involves configuring precise ADC/DMA sampling and applying correct amplitude-invariant transforms.

What is the best way to design ADC DMA timing for dual-shunt current sensing in SVPWM?

Designing ADC DMA timing for SVPWM requires aligning sampling points with the PWM center to avoid switching noise. You must trigger dual-ADC conversions via the STM32G4 timer and use DMA to ensure deterministic, low-latency current reconstruction.

Does this approach support sensorless observers for BLDC motor drives?

Yes, sensorless observers are supported for BLDC motor drives using a Sliding Mode Observer (SMO) paired with a Phase-Locked Loop (PLL). This allows accurate rotor position and speed estimation without physical sensors in your FOC pipeline.

How do I handle emergency protection and safe states in motor drive firmware?

Handling emergency protection in motor drive firmware requires prioritizing Over-Current Protection (OCP) and DC-bus overvoltage handling. You must define explicit safe-state transitions, choosing between High-Z or Active Short Circuit (ASC) behavior during faults.

Why do I need a safety state machine in an STM32G4 FOC implementation?

A safety state machine is needed in STM32G4 FOC implementations to manage fault and abuse-case readiness deterministically. It ensures safe sequencing of control loops and guarantees emergency behavior during critical hardware events.

What are the limitations of using generic FOC templates for production motor drives?

Generic FOC templates lack physically verifiable, timing-aware constraints required for production motor drives. They often fail to address topology-aware current reconstruction, STM32G4 PWM specifics, and explicit safe-state emergency behaviors.