fsm-design

What problem does it solve?

This Skill helps you write and review Verilog/SystemVerilog FSMs that synthesize cleanly without unintended latches, illegal states, or broken handshakes.

Core Features & Use Cases

• Three-process FSM guidance: Separate state register, next-state logic, and output logic to improve linting, reviewability, and correctness.
• Latch and reset correctness: Prevent incomplete case assignments with default-before-case patterns, and ensure deterministic reset behavior.
• Timeout + assertions: Add separate programmable timeout counters and SVA properties (legal-state, liveness, no-deadlock, handshake invariants) to catch issues early in sim and formal.

Quick Start

Use the fsm-design skill when you are implementing or reviewing a SystemVerilog FSM and you want the pattern that prevents latches, handles all states, and includes a practical timeout and SVA assertions.