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functional-verification

Automate UVM-based functional verification workflows for digital chip designs.

180|46|Updated Apr 12, 2026
Search Tags:#regression testing#testbench#uvm#chip design#functional verification
One-click install
npx skills add https://github.com/chuanseng-ng/digital-chip-design-agents --skill functional-verification
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: functional-verification
Source: https://github.com/chuanseng-ng/digital-chip-design-agents/tree/main/plugins/verification/skills/functional-verification
Command: npx skills add https://github.com/chuanseng-ng/digital-chip-design-agents --skill functional-verification

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill requires uvm, verilator, vcs, xcelium, questa, and includes scripts (resource) and references (resource) and assets (resource) components.

What problem does it solve?

This Skill streamlines the UVM-based functional verification process, automating various stages and ensuring efficient verification for digital chip designs.

Core Features & Use Cases

  • Testbench Architecture: Guides the creation of UVM testbenches with a standardized hierarchy and component mapping.
  • Test Planning: Assists in creating a detailed V-Plan for comprehensive test coverage.
  • Directed Tests: Automates the creation and execution of directed tests based on the V-Plan.
  • Constrained Random: Implements constrained random stimulus generation for thorough testing.
  • Coverage Analysis: Provides coverage analysis to ensure all requirements are met.
  • Formal Assist: Integrates formal verification to prove properties and check equivalence.
  • Regression Signoff: Ensures a clean regression by executing a series of regression tests.

Quick Start

Use the functional-verification skill to build a UVM testbench for a specific DUT and run the verification process.

Frequently Asked Questions about functional-verification

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I automate UVM-based functional verification for digital chip designs?▼

You can automate functional verification by generating UVM testbench architectures, creating V-Plans, running directed and constrained-random tests, and analyzing coverage for digital chip designs.

How does constrained random testing work with UVM testbenches?▼

Constrained random testing in UVM testbenches works by automating stimulus generation to thoroughly test digital chip designs, ensuring comprehensive coverage of defined test plan requirements.

Can I use this functional verification workflow with Verilator or Xcelium simulators?▼

Yes, the functional verification workflow supports UVM-based simulators including Verilator, VCS, Xcelium, and Questa to execute testbenches and regression tests for digital chip designs.

What's the best way to integrate formal verification into a UVM regression signoff?▼

Integrate formal verification into UVM regression signoff by proving properties and checking equivalence alongside directed and constrained-random tests to ensure a clean regression for digital chip designs.

How do I create a V-Plan for comprehensive UVM test coverage?▼

Create a V-Plan for comprehensive UVM test coverage by detailing test requirements, mapping them to directed tests, and tracking coverage analysis to ensure all functional verification requirements are met.

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