functional-verification

What problem does it solve?

This Skill streamlines the UVM-based functional verification process, automating various stages and ensuring efficient verification for digital chip designs.

Core Features & Use Cases

• Testbench Architecture: Guides the creation of UVM testbenches with a standardized hierarchy and component mapping.
• Test Planning: Assists in creating a detailed V-Plan for comprehensive test coverage.
• Directed Tests: Automates the creation and execution of directed tests based on the V-Plan.
• Constrained Random: Implements constrained random stimulus generation for thorough testing.
• Coverage Analysis: Provides coverage analysis to ensure all requirements are met.
• Formal Assist: Integrates formal verification to prove properties and check equivalence.
• Regression Signoff: Ensures a clean regression by executing a series of regression tests.

Quick Start

Use the functional-verification skill to build a UVM testbench for a specific DUT and run the verification process.