Automate SystemVerilog simulation with Verilator and emit GateFlow result blocks.
npx skills add https://github.com/codejunkie99/Gateflow-Plugin --skill gf-sim
Please help me install this Agent Skill. Skill: gf-sim Source: https://github.com/codejunkie99/Gateflow-Plugin/tree/main/plugins/gateflow/skills/gf-sim Command: npx skills add https://github.com/codejunkie99/Gateflow-Plugin --skill gf-sim
This Skill automates SystemVerilog simulation by auto-detecting DUT and testbenches, compiling with Verilator, executing the run, and emitting a parseable GateFlow result block.
Use the gf-sim skill to simulate your SV project by providing sources in rtl/ and tb/ and running the simulation.
High-intent search queries and answers about installing and using this skill.
Automating SystemVerilog simulation with Verilator involves auto-detecting DUT and testbench files, compiling sources with tracing, and executing the run to produce a parseable GateFlow result block.
A parseable simulation result block is a standardized output format that enables downstream orchestration tools to automatically consume and evaluate RTL verification test pass and fail statuses.
To auto-detect DUT and testbench files, structure your project by placing RTL modules in the rtl/ directory and testbenches in the tb/ directory before running the simulation flow.
Verilator supports waveform tracing for SystemVerilog testbenches during compilation, enabling waveform generation to help debug and validate RTL modules and assertions.
You can plug SystemVerilog projects into Claude Code to validate RTL modules and verify testbenches with a single command, driving end-to-end compilation and simulation.
Verilator simulation is limited to SystemVerilog projects leveraging Verilator for RTL verification, requiring proper DUT and testbench classification to successfully compile and execute the run.
RedClausCompile and run SystemVerilog simulations with Verilator and report PASS/FAIL/ERROR status.
Snowflake-LabsA concise summary of your roleplay character: name,</name> personality, and/or behavior, formatted as a single string sentence. Typically不超过50字，此处省略
codejunkie99Apply SystemVerilog assertions, covergroups, and testbench templates to validate RTL designs.
codejunkie99Automate SystemVerilog linting, simulation, and analysis task orchestration.
