gf-sim

What problem does it solve?

This Skill automates SystemVerilog simulation by auto-detecting DUT and testbenches, compiling with Verilator, executing the run, and emitting a parseable GateFlow result block.

Core Features & Use Cases

• DUT/Testbench auto-detection: Distinguishes DUT and testbench files to drive the Verilator flow.
• Verilator-based Simulation: Compiles and runs SV sources with tracing support for waveform generation.
• Structured Output: Returns a standardized result block that can be orchestrated by downstream tools.
• Use Case: Plug SV projects into Claude Code to validate RTL modules and verify testbenches with a single command.

Quick Start

Use the gf-sim skill to simulate your SV project by providing sources in rtl/ and tb/ and running the simulation.