What problem does it solve?
When hardware behavior is wrong in simulation, it’s hard for an LLM (and humans) to connect waveform observations back to the right Chisel/Scala sources and RTL ownership. This Skill bridges waveform evidence, emitted RTL hierarchy/ownership, and Scala-first root-cause analysis so debugging is faster and more precise.
Core Features & Use Cases
- Waveform evidence to debug packets: Build time-window “debug packets” from large VCD/FST files, optionally restricted by a focus scope, to surface only relevant signal changes.
- Exact RTL ownership when emitted RTL is available: Parse emitted SystemVerilog (VCD/FST +
build/rtl) to recover exact hierarchical signal owners using rtl_authority.sqlite3.
- Scala/Chisel-first root-cause support: Use
module_type, local_signal_name, and hierarchical matches to locate the best Scala/Chisel candidates and reason about handshake, backpressure, stalls, and state transitions.
Quick Start
Run inspect-inputs by calling: hw debugging waveform inspect-inputs with the required waveform path and the XiangShan-style Scala/Chisel source root.
