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hdl-fault-localization

Analyze Verilog, SystemVerilog, and VHDL failures to produce ranked root-cause hypotheses.

Updated Jul 1, 2026
Search Tags:#debugging#root cause analysis#simulation#rtl#hdl#verilog#fault localization
One-click install
npx skills add https://github.com/AgainstWar/HDL-Repair-Skills --skill hdl-fault-localization
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: hdl-fault-localization
Source: https://github.com/AgainstWar/HDL-Repair-Skills/tree/main/hdl-fault-localization
Command: npx skills add https://github.com/AgainstWar/HDL-Repair-Skills --skill hdl-fault-localization

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

This Skill helps engineers diagnose HDL and RTL failures by turning simulation symptoms, logs, and source code into structured root-cause hypotheses instead of unsupported guesses.

Core Features & Use Cases

  • Systematic Fault Localization: Analyze Verilog, SystemVerilog, and VHDL failures by separating observed behavior from expected behavior and tracing signals back to likely sources.
  • Evidence-Based Hypothesis Ranking: Generate and rank multiple possible causes using logs, code inspection, and waveform observations while avoiding premature fixes.
  • Use Case: When an AXI interface drops transactions or an FSM becomes stuck, use this Skill to identify suspicious modules, signals, and repair directions before changing RTL.

Quick Start

Use the hdl-fault-localization skill to analyze my failing RTL simulation logs and source files and produce a ranked root-cause hypothesis note.

Frequently Asked Questions about hdl-fault-localization

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I find the root cause of Verilog simulation failures?▼

To find the root cause of Verilog simulation failures, analyze failing RTL simulation logs and source files to produce structured, evidence-backed hypotheses. Separate observed behavior from expected behavior and trace signals back to likely faulty modules.

What is the best way to debug SystemVerilog FSM issues?▼

Debugging SystemVerilog FSM issues requires systematic fault localization. Analyze protocol violations and waveform observations to generate and rank multiple possible causes, identifying suspicious modules and repair directions before changing RTL.

Can I use this to analyze VHDL synthesis mismatches?▼

Yes, you can analyze VHDL synthesis mismatches by applying structured fault analysis and signal back-tracing. The Skill examines source code and failures to output machine-parseable diagnostic hypotheses without generating patches.

How do I diagnose AXI protocol violations from simulation logs?▼

Diagnose AXI protocol violations from simulation logs by inspecting waveforms and applying signal back-tracing. The process separates observed behavior from expected behavior to rank possible root causes based on code inspection and log evidence.

Does this approach automatically generate RTL patches for bugs?▼

No, this approach does not generate RTL patches for bugs. It strictly produces machine-parseable diagnostic output and ranked root-cause hypotheses to guide repair directions, ensuring engineers avoid premature fixes without evidence.

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