hdl-fault-localization

What problem does it solve?

This Skill helps engineers diagnose HDL and RTL failures by turning simulation symptoms, logs, and source code into structured root-cause hypotheses instead of unsupported guesses.

Core Features & Use Cases

• Systematic Fault Localization: Analyze Verilog, SystemVerilog, and VHDL failures by separating observed behavior from expected behavior and tracing signals back to likely sources.
• Evidence-Based Hypothesis Ranking: Generate and rank multiple possible causes using logs, code inspection, and waveform observations while avoiding premature fixes.
• Use Case: When an AXI interface drops transactions or an FSM becomes stuck, use this Skill to identify suspicious modules, signals, and repair directions before changing RTL.

Quick Start

Use the hdl-fault-localization skill to analyze my failing RTL simulation logs and source files and produce a ranked root-cause hypothesis note.