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hsb-ip-create-top

Generate fixed-format SystemVerilog FPGA_top.sv scaffolds instantiating HOLOLINK_top from validated HOLOLINK_def.svh files.

3.2k|370|Updated Feb 25, 2026
Search Tags:#systemverilog#FPGA#holoscan#HSB#Code generation#hololink#top-level wrapper
One-click install
npx skills add https://github.com/NVIDIA/skills --skill hsb-ip-create-top
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: hsb-ip-create-top
Source: https://github.com/NVIDIA/skills/tree/main/skills/hsb-ip-create-top
Command: npx skills add https://github.com/NVIDIA/skills --skill hsb-ip-create-top

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve?

Writing a correct top-level SystemVerilog wrapper for the NVIDIA Holoscan Sensor Bridge (HSB) IP requires matching the exact port names, widths, unpacked array shapes, and macro-gated signal groups of HOLOLINK_top, which is error-prone when done by hand. This Skill generates a fixed-format FPGA_top.sv scaffold directly from a validated HOLOLINK_def.svh so the HSB-facing declarations and instantiation stay consistent with the IP revision.

Core Features & Use Cases

  • Fixed-format scaffold generation: Emits FPGA_top.sv with the license header, HOLOLINK_def.svh include, module shell, ordered HSB signal declarations, and HOLOLINK_top instantiation.
  • Macro-driven signal groups: Derives active sensor RX/TX, host, APB, peripheral, GPIO, and PTP groups from the validated defs macros, omitting ports absent under the active macro set.
  • Live source precedence: Prefers a checked-out HOLOLINK_top.sv for port extraction and revision checks, falling back to bundled known-rev references (16'h2604, backward-compatible 16'h2603).
  • Use Case: After validating a HOLOLINK_def.svh with the companion hsb-ip-def skill, ask for a matching top-level wrapper and receive a ready-to-integrate FPGA_top.sv scaffold with TODO placeholders for board-specific connections.

Quick Start

Ask your agent to use hsb-ip-create-top to create an FPGA_top.sv scaffold from your validated HOLOLINK_def.svh file.

Frequently Asked Questions about hsb-ip-create-top

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I create an FPGA_top.sv wrapper for the HSB HOLOLINK_top IP?▼

Provide a validated HOLOLINK_def.svh path or its pasted content, then request the scaffold. The skill derives active signal groups from the defs macros and emits a fixed-format FPGA_top.sv instantiating HOLOLINK_top with correctly shaped ports.

Can I generate FPGA_top.sv without a HOLOLINK_def.svh file?▼

No. A validated HOLOLINK_def.svh is a hard prerequisite. If you do not have one, the skill stops and directs you to the companion hsb-ip-def skill to generate and validate the defs file first.

Which HSB IP revisions does the scaffold generation support?▼

The bundled references cover HSB IP rev 16'h2604 and backward-compatible rev 16'h2603. When a live HOLOLINK_top.sv checkout is available, it takes precedence, and unknown or newer revisions trigger a warning that bundled references may need updating.

Why does FPGA_top.sv show different signal groups for different defs files?▼

Active signal groups are gated by the macros in the validated HOLOLINK_def.svh, such as SENSOR_RX_IF_INST, SPI_INST, or EXT_PTP. Ports absent under the active macro set are omitted from both declarations and the HOLOLINK_top instantiation.

What are the limitations of the generated FPGA_top.sv scaffold?▼

The output is an integration scaffold, not a complete project top: it normally has no top-level ports and uses TODO placeholders for board-specific connections. It does not generate or validate HOLOLINK_def.svh, nor does it add project-specific logic unless explicitly requested.

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