What problem does it solve?
FPGA engineers configuring the NVIDIA Holoscan Sensor Bridge must correctly derive packetizer-related fields in HOLOLINK_def.svh, where wrong values for virtual ports, sort resolution, or cycle counts silently break Sensor RX data manipulation. This Skill derives those fields from the user's actual data layout instead of guesswork.
Core Features & Use Cases
- Packetizer Field Derivation: Computes SIF_RX_PACKETIZER_EN, SIF_RX_VP_COUNT, SIF_RX_SORT_RESOLUTION, SIF_RX_VP_SIZE, and SIF_RX_NUM_CYCLES arrays from stated RX widths and data manipulation intent, with RTL-derived constraint checks.
- Three Output Modes: Standalone SystemVerilog blocks for direct SVH insertion, labeled packetizer_profile_overlay YAML for handoff to the hsb-ip-def skill, and explanation mode for field semantics and architecture questions.
- Live Source Awareness: Prefers live HSB IP RTL (rev 16'h2604, backward-compatible with 16'h2603) over bundled references and warns on unknown revisions.
- Use Case: Given a 512-bit RX0 that must split into four 128-bit virtual streams and a pass-through RX1, the Skill emits enable [1, 0], VP count [4, 1], VP size [128, 32], and matching peer arrays with bypass placeholders.
Quick Start
Ask the agent to use hsb-ip-packetizer to choose packetizer fields for your Sensor RX interfaces, describing each interface's width and whether it needs splitting, rearrangement, replication, or pass-through.