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io-ring-orchestrator-T180

Orchestrate T180 IO Ring generation from requirements to verified schematic and layout.

1|Updated Mar 28, 2026
Search Tags:#workflow-automation#json-generation#virtuoso#io-ring#tsm180#cadence-skills#drc-lvs
One-click install
npx skills add https://github.com/chenzc24/io-ring-orchestrator-T180 --skill io-ring-orchestrator-t180
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: io-ring-orchestrator-T180
Source: https://github.com/chenzc24/io-ring-orchestrator-T180/tree/main
Command: npx skills add https://github.com/chenzc24/io-ring-orchestrator-T180 --skill io-ring-orchestrator-t180

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill requires virtuoso-bridge-lite, python-dotenv, matplotlib, and includes scripts (resource) and references (resource) and assets (resource) components.

What problem does it solve?

Master coordinator for T180 IO Ring generation — orchestrates the full workflow from natural-language requirements to verified schematic and layout, including JSON generation, Cadence SKILL creation, Virtuoso execution, and DRC/LVS verification.

Core Features & Use Cases

  • End-to-end IO Ring generation for 180nm designs, handling drafting, enrichment, and confirmation stages.
  • Automated JSON output and SKILL script generation to drive Virtuoso and Calibre verification.
  • Integrated gate checks, layout generation, and post-processing reports (DRC/LVS) with robust error handling.

Quick Start

Clone the skill repository, configure the environment, and run the 12-step workflow from Step 0 to Step 12.

Frequently Asked Questions about io-ring-orchestrator-T180

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I automate IO Ring generation for TSMC 180nm designs?▼

Automate TSMC 180nm IO Ring generation by orchestrating the end-to-end workflow from natural-language requirements to verified schematics and layouts, including JSON generation, SKILL script creation, and DRC/LVS verification.

Can I run DRC and LVS verification directly within a Cadence Virtuoso workflow?▼

Yes, the workflow integrates Virtuoso execution with Calibre DRC/LVS verification, automating layout generation and post-processing reports with robust error handling across Draft, Enrichment, and Confirmation stages.

What is the best way to map pins and classify voltage domains for an IO Ring?▼

Automate device and voltage-domain classification along with pin mapping by converting requirements into structured JSON outputs, driving the subsequent Cadence SKILL scripts for layout and schematic generation.

Does this IO Ring orchestrator require specific environment dependencies to function?▼

The workflow requires configuring the environment with dependencies like virtuoso-bridge-lite, python-dotenv, and matplotlib to execute the 12-step integration and generate traceable outputs successfully.

How do I execute the 12-step workflow for 180nm IO Ring design?▼

Execute the 12-step workflow by cloning the repository, configuring the environment, and running the integrated process from Step 0 to Step 12 to ensure robust error handling and traceable design outputs.

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