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jlcpcb-alignment

Validate JLCPCB CPL rotation, position corrections, and pin nets for bottom-side components.

2|Updated Feb 8, 2026
Search Tags:#alignment#pcb#dfm#jlcpcb#cpl#pick-and-place#pcba
One-click install
npx skills add https://github.com/pjcau/esp32-emu-turbo --skill jlcpcb-alignment
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: jlcpcb-alignment
Source: https://github.com/pjcau/esp32-emu-turbo/tree/main/.claude/skills/jlcpcb-alignment
Command: npx skills add https://github.com/pjcau/esp32-emu-turbo --skill jlcpcb-alignment

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

Ensures that JLCPCB pick-and-place data (CPL) will correctly position and orient bottom-side ICs and connectors, preventing misaligned parts, rotated footprints, and pin-to-net mismatches before ordering PCBA.

Core Features & Use Cases

  • Rotation alignment checks: Compares CPL rotation and mirroring against KiCad footprint model rotations to detect orientation mismatches with a per-pin error tolerance.
  • Position correction validation: Verifies CPL position corrections against board reference positions to catch missing or incorrect translation offsets.
  • Pin net assignment verification: Confirms that routed pin nets in the PCB match the expected routing module nets to detect swaps caused by rotation/mirror bugs.
  • Use Case: Run this verification as a pre-order gate for JLCPCB PCBA batches or after changing CPL generation parameters to avoid assembly faults.

Quick Start

Run the batch alignment tests from the project root using the repository's verification scripts to validate CPL rotation, position corrections, and pin net assignments.

Frequently Asked Questions about jlcpcb-alignment

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I verify JLCPCB pick-and-place alignment for bottom-side components?▼

Verify JLCPCB pick-and-place alignment by running deterministic validation scripts that check CPL rotation, position corrections, and pin net assignments for bottom-side ICs and connectors before ordering PCBA.

What is CPL rotation matching and how does it prevent PCBA assembly faults?▼

CPL rotation matching compares pick-and-place rotation and mirroring against KiCad footprint rotations to detect orientation mismatches, preventing misaligned parts and pin-to-net swaps during PCB assembly.

How do I validate CPL position corrections before submitting a JLCPCB PCBA order?▼

Validate CPL position corrections by checking them against board reference positions to catch missing or incorrect translation offsets, ensuring accurate component placement for JLCPCB PCBA batches.

Can I use this verification for KiCad PCB projects adjusting CPL generation parameters?▼

Yes, you can use this verification for KiCad PCB projects adjusting CPL generation parameters, as it confirms per-pin net assignment consistency with a maximum per-pin error threshold of 0.1mm.

Why does my pick-and-place data have pin-to-net mismatches after adjusting footprint rotation?▼

Pin-to-net mismatches occur when CPL rotation or mirror adjustments introduce bugs, which verification catches by confirming routed pin nets match expected routing module nets within a 0.1mm error tolerance.

What is the maximum per-pin error threshold for JLCPCB pick-and-place validation?▼

The maximum per-pin error threshold for JLCPCB pick-and-place validation is 0.1mm, ensuring per-pin net assignment consistency and accurate alignment for bottom-side ICs and connectors.

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