jlcpcb-alignment

What problem does it solve?

Ensures that JLCPCB pick-and-place data (CPL) will correctly position and orient bottom-side ICs and connectors, preventing misaligned parts, rotated footprints, and pin-to-net mismatches before ordering PCBA.

Core Features & Use Cases

• Rotation alignment checks: Compares CPL rotation and mirroring against KiCad footprint model rotations to detect orientation mismatches with a per-pin error tolerance.
• Position correction validation: Verifies CPL position corrections against board reference positions to catch missing or incorrect translation offsets.
• Pin net assignment verification: Confirms that routed pin nets in the PCB match the expected routing module nets to detect swaps caused by rotation/mirror bugs.
• Use Case: Run this verification as a pre-order gate for JLCPCB PCBA batches or after changing CPL generation parameters to avoid assembly faults.

Quick Start

Run the batch alignment tests from the project root using the repository's verification scripts to validate CPL rotation, position corrections, and pin net assignments.