jtagprobe

Probe IoT targets for exposed SWD and JTAG debug interfaces using a SEGGER J-Link.

824|126|Updated Nov 17, 2025
One-click install
npx skills add https://github.com/BrownFineSecurity/iothackbot --skill jtagprobe
Or copy as Structured Prompt for Agent
Please help me install this Agent Skill.
Skill: jtagprobe
Source: https://github.com/BrownFineSecurity/iothackbot/tree/main/skills/jtagprobe
Command: npx skills add https://github.com/BrownFineSecurity/iothackbot --skill jtagprobe

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

Hardware security testers need to know whether an embedded target's on-chip debug port is exposed, locked, or fused off, but manually driving J-Link sessions and interpreting DPIDR/IDCODE responses is slow and error-prone.

Core Features & Use Cases

  • Automated interface sweep: Sweeps SWD then JTAG across multiple clock speeds (4000/1000/100 kHz) with a JTAG chain auto-scan fallback.
  • Three-state classification: Classifies targets as OPEN (full halt and memory access), LOCKED (readout protection like STM32 RDP, NXP CRP, Nordic APPROTECT), or DEAD (no response).
  • Vendor identification and evidence capture: Decodes DPIDR/IDCODE JEP106 designer fields to identify silicon vendors and saves per-attempt JLinkExe logs for pentest writeups.
  • Use Case: During an IoT pentest, run the probe against an unknown STM32-based board to confirm the debug port responds, capture the all-0xFF flash reads proving RDP is engaged, and document the finding under CWE-1191.

Quick Start

Ask the assistant to test the connected target for exposed JTAG and SWD debug interfaces and save the evidence logs to a timestamped directory.

Frequently Asked Questions about jtagprobe

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I test if an IoT device has an exposed JTAG or SWD debug port?

Connect a SEGGER J-Link to the target's debug header and run jtagprobe with default settings. It sweeps SWD then JTAG at multiple clock speeds, halts the CPU, reads memory, and classifies the port as OPEN, LOCKED, or DEAD.

What hardware do I need for SWD/JTAG debug interface testing?

You need a SEGGER J-Link probe connected via USB, JLinkExe installed and on PATH, and the target wired to the J-Link 20-pin or 10-pin Cortex Debug header. Confirm SWDIO/SWCLK or TDI/TDO/TMS/TCK pin identification before powering the target.

What does a LOCKED classification mean on a debug port scan?

LOCKED means the debug port responds with a valid DPIDR or IDCODE but memory reads fail or return 0xFFFFFFFF sentinels. This indicates readout protection such as STM32 RDP, NXP CRP, or Nordic APPROTECT is engaged, though the port itself remains exposed.

Can jtagprobe identify the chip vendor from a debug probe?

Yes, it decodes the JEP106 designer field from DPIDR or IDCODE values to identify vendors such as STMicroelectronics, NXP, Nordic, and TI. Passing --device with a known chip name like STM32F407VG improves halt and memory test accuracy.

Does jtagprobe work without physical access to the device?

No, it requires physical access to the debug header and a wired J-Link probe. It is not a network or pcap-based check, and it does not perform unlock or mass-erase operations, which are destructive and out of scope.