kicad-spec-extractor

Convert high-level PCB design intent into a structured YAML/JSON specification.

15|1|Updated Oct 23, 2025
One-click install
npx skills add https://github.com/synqing/K1.hardware --skill kicad-spec-extractor
Or copy as Structured Prompt for Agentโ–ผ
Please help me install this Agent Skill.
Skill: kicad-spec-extractor
Source: https://github.com/synqing/K1.hardware/tree/main/.claude/skills/kicad-spec-extractor
Command: npx skills add https://github.com/synqing/K1.hardware --skill kicad-spec-extractor

SYSTEM DOCUMENTATION & REQUIREMENTS

๐Ÿ’ก This Skill requires python3.

What problem does it solve?

Translating high-level design ideas into detailed, actionable PCB specifications is a critical but often manual and inconsistent step. This Skill automates the conversion of design intent into a structured, version-controlled YAML/JSON specification, ensuring all downstream PCB pipeline stages operate from a single source of truth, reducing ambiguity and accelerating the design process.

Core Features & Use Cases

  • Intent-to-Spec Conversion: Parses user prompts or design documents to extract board type, form factor, layer count, major components, and electrical constraints.
  • Structured Spec Generation: Creates a comprehensive design-spec.yaml with fields for electrical, mechanical, component, and manufacturing details.
  • Validation & Feasibility Checks: Automatically verifies the completeness, feasibility, and consistency of the generated specification.
  • Use Case: Kickstart a new PCB design by automatically generating a detailed specification, ensure all design constraints are captured and validated early, or maintain a reproducible record of design decisions.

Quick Start

Example: Design spec for a 4-layer LED driver

design: name: "K1 Lightwave Controller" description: "Dual ESP32-S3 audio-reactive LED driver" pcb: layer_count: 4 substrate: "FR-4, 1.6mm" min_trace_width: 0.15 # mm manufacturer: target: "jlcpcb" class: "standard"

Frequently Asked Questions about kicad-spec-extractor

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I convert PCB design intent into a structured specification?โ–ผ

Design specification extraction converts high-level board requirements into a detailed YAML/JSON spec capturing form factor, layer count, components, electrical constraints, and manufacturing targets. This automates the translation from design ideas to a version-controlled single source of truth for PCB pipelines, reducing manual work and ambiguity.

What information gets extracted into a PCB design spec?โ–ผ

The extraction captures board name and description, layer count and substrate type, trace width and electrical constraints, component requirements, and manufacturing class and target. The resulting spec includes mechanical, electrical, component, and manufacturing details in structured YAML/JSON format for downstream validation and synthesis.

Can I automate PCB specification generation from design documents?โ–ผ

Yes. The tool parses user prompts or design documents to extract board characteristics and constraints automatically, then generates a comprehensive specification with validation and feasibility checks built in. This eliminates manual transcription and ensures all design decisions are captured consistently and reproducibly.

How does specification validation work in the PCB design process?โ–ผ

Validation verifies completeness, feasibility, and consistency of the generated specification before downstream stages run. Automated checks catch missing constraints, conflicting requirements, and manufacturing feasibility issues early, preventing costly rework in synthesis, verification, and deployment workflows.

What's the benefit of version-controlling PCB specifications?โ–ผ

Version-controlled YAML/JSON specs create an auditable record of design decisions and evolving requirements. This enables reproducible builds, simplifies collaboration across design teams, and provides a reliable baseline for traceability when specifications change or designs iterate.