krnopt-hw-aware-optimization

Hardware-aware CUDA optimization maps your kernel's workload shape to target GPU compute capabilities, selecting an architecture branch like pre-SM90, SM90 Hopper, or SM100 Blackwell to maximize throughput with appropriate hardware surfaces.

Optimizing MoE and FP8 kernels on SM90 Hopper requires domain-driven planning that maps data-movement patterns to specific code shapes like TMA and WGMMA, providing actionable code-path recommendations and measurable validation steps for profiling.

Mapping workload characteristics to hardware surfaces involves identifying the target compute capability and specifying candidate surfaces like TMA, WGMMA, TMEM, CLC, or PDL to construct a structured plan linking hardware targets to concrete code shapes.

Kernel optimization strategy differs across architectures by recommending specific architecture branches, separating SM90 Hopper from consumer Blackwell to select the correct hardware-aware optimization path and candidate surfaces for target validation.

Specifying evidence and next steps for profiling confirms the hardware utilization hypothesis, ensuring that the selected architecture branch and code shapes like TMA actually maximize kernel throughput on the target GPU.

Grouped GEMM optimization on SM100 Blackwell benefits from hardware-aware planning that selects appropriate code paths and surfaces like TMEM, ensuring the CUTLASS-based implementation matches the target architecture's unique compute capabilities.