logic-synthesis

Synthesize RTL to gate-level netlists with SDC validation and LEC verification.

180|46|Updated Apr 12, 2026

Search Tags:#netlist #RTL #logic synthesis #SDC constraint #LEC equivalence

Ready to run

npx skills add https://github.com/chuanseng-ng/digital-chip-design-agents --skill logic-synthesis

💬 Prompt for ChatGPT / Claude Chat▼

Please help me install this Agent Skill.
Skill: logic-synthesis
Source: https://github.com/chuanseng-ng/digital-chip-design-agents/tree/main/plugins/synthesis/skills/logic-synthesis
Command: npx skills add https://github.com/chuanseng-ng/digital-chip-design-agents --skill logic-synthesis

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill requires yosys, surelog, abc, dc_shell, genus, fc_shell, and includes scripts (resource) and references (resource) and assets (resource) components.

What problem does it solve?

Logic synthesis transforms high-level RTL (Register Transfer Level) code into gate-level netlists, optimizing for timing, area, and power. This skill streamlines this process with SDC constraint validation, netlist quality checks, and LEC equivalence verification.

Core Features & Use Cases

RTL to Netlist Conversion: Transforms RTL code into gate-level netlists for ASIC implementation.
SDC Constraint Validation: Ensures SDC constraints are correctly set up for timing and other constraints.
Netlist Quality Checks: Verifies the netlist for black boxes, combinational loops, and scan chain integrity.
LEC Equivalence Verification: Ensures RTL and netlist are functionally equivalent.
Use Case: Synthesize a complex RTL design for an ASIC, ensuring the synthesized netlist meets all design and timing constraints.

Quick Start

Use the logic-synthesis skill to synthesize your RTL design 'my_rtl_design.sv'.

Frequently Asked Questions about logic-synthesis

High-intent search queries and answers about installing and using this skill.

FAQPage Schema

How do I synthesize RTL to a gate-level netlist for an ASIC design flow?▼

To synthesize RTL to a gate-level netlist, this skill transforms Register Transfer Level code into optimized gates using EDA tools like Yosys and Genus, ensuring timing, area, and power constraints are met for ASIC implementation.

What is logic synthesis LEC equivalence verification and when is it needed?▼

LEC equivalence verification checks that the RTL source and synthesized gate-level netlist are functionally identical. It is needed after logic synthesis to confirm the conversion process preserved the original design logic.

Does this logic synthesis flow support SDC constraint validation?▼

Yes, this logic synthesis flow supports SDC constraint validation. It verifies that timing and design constraints are correctly established before finalizing the gate-level netlist for the ASIC implementation.

How do I check netlist quality for black boxes and combinational loops after synthesis?▼

To check netlist quality, this skill performs automated verification for black boxes, combinational loops, and scan chain integrity. This ensures the synthesized gate-level netlist is structurally sound and ready for physical design.

Can I use Yosys and Surelog for RTL to netlist conversion in this flow?▼

Yes, you can use Yosys and Surelog for RTL to netlist conversion. The skill integrates these tools along with ABC, dc_shell, Genus, and fc_shell to execute the logic synthesis and verification workflow.