logic-synthesis

What problem does it solve?

Logic synthesis transforms high-level RTL (Register Transfer Level) code into gate-level netlists, optimizing for timing, area, and power. This skill streamlines this process with SDC constraint validation, netlist quality checks, and LEC equivalence verification.

Core Features & Use Cases

• RTL to Netlist Conversion: Transforms RTL code into gate-level netlists for ASIC implementation.
• SDC Constraint Validation: Ensures SDC constraints are correctly set up for timing and other constraints.
• Netlist Quality Checks: Verifies the netlist for black boxes, combinational loops, and scan chain integrity.
• LEC Equivalence Verification: Ensures RTL and netlist are functionally equivalent.
• Use Case: Synthesize a complex RTL design for an ASIC, ensuring the synthesized netlist meets all design and timing constraints.

Quick Start

Use the logic-synthesis skill to synthesize your RTL design 'my_rtl_design.sv'.