low-power-design

What problem does it solve?

This Skill helps you reduce chip or FPGA power by guiding correct low-power RTL patterns and UPF power-management specifications that meet real power budgets.

Core Features & Use Cases

• Clock gating & activity reduction: Add safe clock/operand gating to reduce dynamic switching without breaking synchronous design assumptions.
• Power-domain specification with UPF: Define power domains, isolation, and retention so powered-down logic behaves correctly at boundaries.
• Voltage scaling & power analysis: Select multi-Vt/DVFS approaches and validate via PrimeTime PX-style switching/leakage power reporting.

Quick Start

Tell your AI agent: “Update my RTL and UPF to add clock gating and operand isolation, define the power domains with isolation/retention for UPF, and then suggest a PrimeTime PX power-analysis report plan to verify we meet the budget.”