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KishoreDamam
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low-power-design

Add clock/operand gating and UPF power domains for low-power FPGA or SoC designs.

1|1|Updated Jan 29, 2026
Search Tags:#power analysis#low power#clock gating#UPF#voltage scaling#PrimeTime PX#operand isolation
One-click install
npx skills add https://github.com/KishoreDamam/VLSI-agkit --skill low-power-design
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: low-power-design
Source: https://github.com/KishoreDamam/VLSI-agkit/tree/main/.agent/skills/low-power-design
Command: npx skills add https://github.com/KishoreDamam/VLSI-agkit --skill low-power-design

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve?

This Skill helps you reduce chip or FPGA power by guiding correct low-power RTL patterns and UPF power-management specifications that meet real power budgets.

Core Features & Use Cases

  • Clock gating & activity reduction: Add safe clock/operand gating to reduce dynamic switching without breaking synchronous design assumptions.
  • Power-domain specification with UPF: Define power domains, isolation, and retention so powered-down logic behaves correctly at boundaries.
  • Voltage scaling & power analysis: Select multi-Vt/DVFS approaches and validate via PrimeTime PX-style switching/leakage power reporting.

Quick Start

Tell your AI agent: “Update my RTL and UPF to add clock gating and operand isolation, define the power domains with isolation/retention for UPF, and then suggest a PrimeTime PX power-analysis report plan to verify we meet the budget.”

Frequently Asked Questions about low-power-design

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I add clock gating and operand isolation to reduce dynamic power in RTL?▼

Clock gating and operand isolation reduce dynamic switching power by inserting safe gating primitives into RTL. This prevents synchronous design violations while lowering switching activity across inactive logic blocks.

How do I define power domains with isolation and retention using UPF?▼

UPF defines power domains, isolation, and retention to ensure powered-down logic behaves correctly at boundaries. Correct UPF definitions prevent functional regressions during multi-voltage or multi-domain integration.

Can I use PrimeTime PX for post-implementation power analysis and validation?▼

PrimeTime PX validates post-implementation power by generating switching and leakage power reports. This verifies your low-power RTL and UPF strategy meets real power budgets without causing sign-off regressions.

What's the best way to implement voltage scaling and avoid RTL anti-patterns?▼

Voltage scaling implementation selects multi-Vt or DVFS approaches while avoiding common RTL anti-patterns. This balances timing and power trade-offs to prevent functional regressions during power-aware validation.

Why do I need glitch-safe clock-control primitives for low-power design?▼

Glitch-safe clock-control primitives are required to prevent timing violations when adding clock gating directives. They ensure low-power transformations do not introduce functional hazards or break synchronous assumptions.

Does low-power FPGA design require UPF definitions for multi-domain integration?▼

Multi-domain FPGA integration requires correct UPF definitions for isolation and retention. Power-aware validation across timing and power trade-offs ensures powered-down logic behaves correctly at domain boundaries.

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